Document Number: MC33899 Freescale Semiconductor Rev. 4.0, 5/2010 Advance Information Programmable H-Bridge Power IC 33899 The 33899 is designed to drive a DC motor in both forward and reverse shaft rotation under pulse-width modulation (PWM) control of speed and torque. A current mirror output provides an analog PROGRAMMABLE H-BRIDGE POWER IC feedback signal proportional to the load current. A serial peripheral interface (SPI) is used to select slew rate control, current compensation limits and to read diagnostic status (faults) of the H- Bridge drive circuits. SPI diagnostic reporting includes open circuit, short-circuit to VIGNP, short-circuit to ground, die temperature range, and under-voltage on VIGNP. Features Drives inductive loads in a full H-Bridge configuration VW SUFFIX (Pb-FREE) Current mirror output signal (gain selectable via external resistor) 98ASH70693A 30-PIN HSOP Short-circuit current limiting Thermal shutdown (outputs latched off until reset via the SPI) Internal charge pump circuit for the internal high side MOSFETs ORDERING INFORMATION SPI-selectable slew rate control and current limit control Temperature Over-temperature shutdown Device Package Range (T ) A Outputs can be disabled to high-impedance state PWM-able up to 11 kHz 3.0 A MC33899VW/R2 -40C to 125C 30 HSOP Synchronous rectification control of the high side MOSFETs Low RDS(ON) outputs at high junction temperature (< 165 m TA = 125C, VIGNP = 6.0 V) Outputs survive shorts to -1.0 V Pb-free packaging designated by suffix code VW V V 33899 DDL +5.0 V IGNP VIGNP REDIS VCC VDDQ CRES CSNS VCCL FWD S1 REV PWM EN1 S0 EN2 MCU CS RS SCLK DI D0 LSCMP GND Figure 1. 33899 Simplified Application Diagram This document contains certain information on a new product. Specifications and information herein are subject to change without notice. Freescale Semiconductor, Inc., 2007-2010. All rights reserved.INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM VIGNP Charge CRES Pump To Gate Drives M1 M3 S1 VCC +3.3 V Current Internal Sense, VCCL Regulator Limitation, and Mirror CSNS S0 M2 M4 Gate Drives PWM REDIS Override LSCMP FWD Direction REV Baseline and PWM PWM RS Slew Rate Control Set EN1 EN2 VDDQ SCLK Temperature Command, Fault, and CS Sense and Temperature Register Shutdown DI DO GND Figure 2. 33899 Simplified Internal Block Diagram 33899 Analog Integrated Circuit Device Data 2 Freescale Semiconductor