MMPF0100FBANES

NXP Semiconductors Document Number: MMPF0100 Rev. 18, 7/2019 Data sheet: Technical Data 14 channel configurable power PF0100 management integrated circuit The PF0100 SMARTMOS power management integrated circuit (PMIC) provides a highly programmable/ configurable architecture, with fully integrated POWER MANAGEMENT power devices and minimal external components. With up to six buck converters, six linear regulators, RTC supply, and coin-cell charger, the PF0100 can provide power for a complete system, including applications processors, memory, and system peripherals, in a wide range of applications. With on-chip one time programmable (OTP) memory, the PF0100 is available in pre-programmed standard versions, or non-programmed to support custom programming. The PF0100 is defined to power an entire embedded MCU platform solution such as i.MX 6 based eReader, IPTV, medical monitoring, and home/factory automation. EP SUFFIX (E-TYPE) ES SUFFIX (WF-TYPE) 98ASA00405D 98ASA00589D 56 QFN 8X8 56 QFN 8X8 Features: Applications: Four to six buck converters, depending on configuration Tablets Single/Dual phase/ parallel options IPTV DDR termination tracking mode option eReaders Boost regulator to 5.0 V output Set top boxes Six general purpose linear regulators Industrial control Programmable output voltage, sequence, and timing Medical monitoring OTP (one time programmable) memory for device configuration Home automation/ alarm/ energy management Coin cell charger and RTC supply DDR termination reference voltage Power control logic with processor interface and event detection 2 I C control Individually programmable ON, OFF, and standby modes PF0100 i.MX 6X VREFDDR DDR MEMORY DDR Memory SW4 INTERFACE 1000 mA SW3A/B 2500 mA SW1A/B Processor Core 2500 mA Voltages SW1C 2000 mA External AMP Microphones SW2 Speakers 2000 mA SATA - FLASH SD-MMC/ SATA NAND - NOR NAND Mem. HDD SWBST Interfaces Audio 600 mA Codec Control Signals Parallel control/GPIOS 2 2 I C Communication I C Communication Sensors VGEN1 Camera 100 mA Camera VGEN2 GPS WAM 250 mA MIPI GPS uPCIe VGEN3 MIPI 100 mA VGEN4 HDMI 350 mA LDVS Display VGEN5 100 mA USB LICELL VGEN6 Ethernet Charger 200 mA CAN Main Supply COINCELL 2.8 4.5 V Front USB Rear Seat Rear USB Cluster/HUD POD Infotaiment POD Figure 1. Simplified application diagram NXP B.V. 2019.Table of Contents 1 Orderable parts 4 2 Internal block diagram . 6 3 Pin connections 7 3.1 Pinout diagram . 7 3.2 Pin definitions 8 4 General product characteristics . 10 4.1 Absolute maximum ratings . 10 4.2 Thermal characteristics . 11 4.2.1 Power dissipation 11 4.3 Electrical characteristics . 12 4.3.1 General specifications . 12 4.3.2 Current consumption 13 5 General description 15 5.1 Features . 15 5.2 Functional block diagram 16 5.3 Functional description 16 5.3.1 Power generation 16 5.3.2 Control logic 16 6 Functional block requirements and behaviors 18 6.1 Start-up 18 6.1.1 Device start-up configuration 18 6.1.2 One time programmability (OTP) 21 6.1.3 OTP prototyping . 23 6.1.4 Reading OTP fuses . 23 6.1.5 Programming OTP fuses . 23 6.2 16 MHz and 32 kHz clocks . 24 6.2.1 Clock adjustment . 24 6.3 Bias and references block description 24 6.3.1 Internal core voltage references . 24 6.3.2 VREFDDR voltage reference . 25 6.4 Power generation 28 6.4.1 Modes of operation . 28 6.4.2 State machine flow summary . 30 6.4.3 Power tree 32 6.4.4 Buck regulators 34 6.4.5 Boost regulator 77 6.4.6 LDO regulators description . 80 6.4.7 VSNVS LDO/switch . 95 6.5 Control interface I2C block description . 100 6.5.1 I2C device ID . 100 6.5.2 I2C operation . 100 6.5.3 Interrupt handling . 101 6.5.4 Interrupt bit summary 101 6.5.5 Specific registers 106 6.5.6 Register bitmap . 107 PF0100 2 NXP Semiconductors