MPC8315ECVRAGDA

Document Number: MPC8315EEC Freescale Semiconductor Rev. 2, 11/2011 Data Sheet: Technical Data MPC8315E PowerQUICC II Pro Processor Hardware Specifications Contents This document provides an overview of the MPC8315E 1. Overview . 2 PowerQUICC II Pro processor features, including a block 2. MPC8315E Features 2 diagram showing the major functional components. The 3. Electrical Characteristics 8 MPC8315E contains a core built on Power Architecture 4. Power Characteristics 14 5. Clock Input Timing 15 technology. It is a cost-effective, low-power, highly 6. RESET Initialization . 17 integrated host processor that addresses the requirements of 7. DDR and DDR2 SDRAM . 18 several storage, consumer, and industrial applications, 8. DUART . 24 9. Ethernet: Three-Speed Ethernet, MII Management . 24 including main CPUs and I/O processors in network attached 10. USB 39 storage (NAS), voice over IP (VoIP) router/gateway, 11. Local Bus . 41 intelligent wireless LAN (WLAN), set top boxes, industrial 12. JTAG . 44 2 controllers, and wireless access points. The MPC8315E 13. I C . 47 14. PCI 49 extends the PowerQUICC II Pro family, adding higher CPU 15. High-Speed Serial Interfaces (HSSI) 51 performance, new functionality, and faster interfaces while 16. PCI Express 61 addressing the requirements related to time-to-market, price, 17. Serial ATA (SATA) 68 18. Timers 70 power consumption, and package size. Note that while the 19. GPIO . 71 MPC8315E supports a security engine, the MPC8315 does 20. IPIC 72 not. 21. SPI . 72 22. TDM . 74 23. Package and Pin Listings . 76 24. Clocking 90 25. Thermal . 95 26. System Design Information 100 27. Ordering Information . 103 28. Revision History . 105 Freescale Semiconductor, Inc., 2011. All rights reserved.Overview 1 Overview The MPC8315E incorporates the e300c3 (MPC603e-based) core, which includes 16 Kbytes of L1 instruction and data caches, on-chip memory management units (MMUs), and floating-point support. In addition to the e300 core, the SoC platform includes features such as dual enhanced three-speed 10, 100, 1000 Mbps Ethernet controllers (eTSECs) with SGMII support, a 32- or 16-bit DDR1/DDR2 SDRAM memory controller, dual SATA 3 Gbps controllers (MPC8315E-specific), a security engine to accelerate control and data plane security protocols, and a high degree of software compatibility with previous-generation PowerQUICC processor-based designs for backward compatibility and easier software migration. The MPC8315E also offers peripheral interfaces such as a 32-bit PCI interface with up to 66 MHz operation, 16-bit enhanced local bus interface with up to 66 MHz operation, TDM interface, and USB 2.0 with an on-chip USB 2.0 PHY. The MPC8315E offers additional high-speed interconnect support with dual integrated SATA 3 Gbps interfaces and dual single-lane PCI Express interfaces. When not used for PCI Express, the SerDes interface may be configured to support SGMII. The MPC8315E security engine (SEC 3.3) allows CPU-intensive cryptographic operations to be offloaded from the main CPU core. This figure shows a block diagram of the MPC8315E. MPC8315E e300c3 Core with Power Management 16-KB 16-KB DUART D-Cache I-Cache 2 I C Enhanced Interrupt Timers DDR1/DDR2 Security Local Bus, FPU Controller TDM Controller Engine 3.3 GPIO SPI I/O USB 2.0 HS PCI PCI Sequencer eTSEC SATA SATA eTSEC Host/Device/OTG Express Express (IOS) On-Chip x1 x1 RGMII, (R)MII RGMII, (R)MII PHY PHY ULPI RTBI, SGMII RTBI, SGMII HS PHY DMA Note: The MPC8315 do not include a security engine. PCI Figure 1. MPC8315E Block Diagram 2 MPC8315E Features The following features are supported in the MPC8315E. 2.1 e300 Core The e300 core has the following features: Operates at up to 400 MHz MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2 2 Freescale Semiconductor