MPC8533EVJANGA

Document Number: MPC8533EEC Freescale Semiconductor Rev. 8, 09/2015 Technical Data MPC8533E PowerQUICC III Integrated Processor Hardware Specifications Contents 1 MPC8533E Overview 1. MPC8533E Overview . 1 2. Electrical Characteristics 8 This section provides a high-level overview of MPC8533E 3. Power Characteristics 13 features. Figure 1 shows the major functional units within 4. Input Clocks . 13 5. RESET Initialization . 16 the device. 6. DDR and DDR2 SDRAM . 16 7. DUART . 22 8. Enhanced Three-Speed Ethernet (eTSEC), 1.1 Key Features MII Management 23 9. Ethernet Management Interface Electrical The following list provides an overview of the device feature Characteristics .37 set: 10. Local Bus . 39 11. Programmable Interrupt Controller . 50 High-performance, 32-bit core enhanced by 12. JTAG . 51 resources for embedded cores defined by the Power 2 13. I C . 53 ISA, and built on Power Architecture technology: 14. GPIO . 55 15. PCI 56 32-Kbyte L1 instruction cache and 32-Kbyte L1 16. High-Speed Serial Interfaces (HSSI) 58 data cache with parity protection. Caches can be 17. PCI Express 68 locked entirely or on a per-line basis, with 18. Package Description . 76 19. Clocking 88 separate locking for instructions and data. 20. Thermal . 91 Signal-processing engine (SPE) APU (auxiliary 21. System Design Information 100 processing unit). Provides an extensive 22. Device Nomenclature . 109 23. Document Revision History 111 instruction set for vector (64-bit) integer and fractional operations. These instructions use both the upper and lower words of the 64-bit GPRs as they are defined by the SPE APU. Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 2008-2011, 2014-2015 Freescale Semiconductor, Inc. All rights reserved.MPC8533E Overview Double-precision floating-point APU. Provides an instruction set for double-precision (64-bit) floating-point instructions that use the 64-bit GPRs. 36-bit real addressing Embedded vector and scalar single-precision floating-point APUs. Provide an instruction set for single-precision (32-bit) floating-point instructions. Memory management unit (MMU). Especially designed for embedded applications. Supports 4-Kbyte4-Gbyte page sizes. Enhanced hardware and software debug support Performance monitor facility that is similar to, but separate from, the device performance monitor The e500 defines features that are not implemented on this device. It also generally defines some features that this device implements more specifically. An understanding of these differences can be critical to ensure proper operations. 256-Kbyte L2 cache/SRAM Flexible configuration Full ECC support on 64-bit boundary in both cache and SRAM modes Cache mode supports instruction caching, data caching, or both. External masters can force data to be allocated into the cache through programmed memory ranges or special transaction types (stashing). 1, 2, or 4 ways can be configured for stashing only. Eight-way set-associative cache organization (32-byte cache lines) Supports locking entire cache or selected lines. Individual line locks are set and cleared through Book E instructions or by externally mastered transactions. Global locking and flash clearing done through writes to L2 configuration registers Instruction and data locks can be flash cleared separately. SRAM features include the following: I/O devices access SRAM regions by marking transactions as snoopable (global). Regions can reside at any aligned location in the memory map. Byte-accessible ECC is protected using read-modify-write transaction accesses for smaller-than-cache-line accesses. Address translation and mapping unit (ATMU) Eight local access windows define mapping within local 36-bit address space. Inbound and outbound ATMUs map to larger external address spaces. Three inbound windows plus a configuration window on PCI and PCI Express Four outbound windows plus default translation for PCI and PCI Express DDR/DDR2 memory controller Programmable timing supporting DDR and DDR2 SDRAM 64-bit data interface MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 8 2 Freescale Semiconductor