INTEGRATED CIRCUITS
74F125, 74F126
Quad buffers (3-State)
Product specification 1989 March 28
IC15 Data Handbook
Philips Semiconductors Product specification
Quad buffers (3-State) 74F125, 74F126
FEATURE ORDERING INFORMATION
High impedance NPN base inputs for reduced loading
COMMERCIAL RANGE
V = 5V 10%,
(20A in High and Low states) DESCRIPTION PKG DWG #
CC
T = 0C to +70C
amb
14-pin plastic DIP N74F125N, N74F126N SOT27-1
TYPICAL TYPICAL
PROPAGATION SUPPLY CURRENT
TYPE
14-pin plastic SO N74F125D, N74F126D SOT108-1
DELAY (TOTAL)
74F125 5.0ns 23mA
74F126 5.0ns 26mA
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW
D0D3 Data inputs 1.0/0.033 20A/20A
OE0OE3 Output Enable inputs (active Low), 74F125 1.0/0.033 20A/20A
OE0OE3 Output Enable inputs (active High), 74F126 1.0/0.033 20A/20A
Q0Q3 Data outputs 750/106.7 15mA/64mA
NOTE: One (1.0) FAST unit load is defined as: 20A in the High state and 0.6mA in the Low state.
PIN CONFIGURATIONS
74F125 74F126
OE0 1 14
OE0 1 14 V V
CC
CC
D0 2 13 OE3 D0 2 13 OE3
Q0 3 12 D3 Q0 3 12 D3
OE1 4 11 Q3 OE1 4 11 Q3
D1 5 10 OE2 D1 5 10 OE2
Q1 6 9 D2 Q1 6 9 D2
GND 7 8 Q2 GND 7 8 Q2
SF00117 SF00118
LOGIC SYMBOLS
74F126
74F125
25 912
25 912
D0 D1 D2 D3
D0 D1 D2 D3
1
OE0 1
OE0
4 OE1
4 OE1
10 OE2
10 OE2
13 OE3
13 OE3
Q1 Q1
Q0 Q0 Q1 Q1
Q0 Q0
36 811
V = Pin 14 36 811
CC V = Pin 14
CC
GND = Pin 7
GND = Pin 7
SF00119 SF00120
2
March 28, 1989 8530341 96146