PCF8593 Low power clock and calendar Rev. 5 24 January 2020 Product data sheet 1. General description 1 The PCF8593 is a CMOS clock and calendar circuit, optimized for low power consumption. Addresses and data are transferred serially via the two-line bidirectional 2 I C-bus. The built-in word address register is incremented automatically after each written or read data byte. The built-in 32.768 kHz oscillator circuit and the first 8 bytes of the RAM are used for the clock, calendar, and counter functions. The next 8 bytes can be programmed as alarm registers or used as free RAM space. 2. Features and benefits 2 I C-bus interface operating supply voltage: 2.5 V to 6.0 V Clock operating supply voltage 1.0 V to 6.0 V at 0 Cto +70 C 8 bytes scratchpad RAM (when alarm not used) Data retention voltage: 1.0 V to 6.0 V 2 External RESET input resets I C interface only Operating current (at f = 0 Hz, 32 kHz time base, V = 2.0 V): typical 1 A SCL DD Clock function with four year calendar Universal timer with alarm and overflow indication 24 hour or 12 hour format 32.768 kHz or 50 Hz time base 2 Serial input and output bus (I C-bus) Automatic word address incrementing Programmable alarm, timer, and interrupt function Space-saving SO8 package Slave addresses: A3h for reading, A2h for writing 1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 13.PCF8593 NXP Semiconductors Low power clock and calendar 3. Ordering information Table 1. Ordering information Type number Topside Package marking Name Description Version PCF8593T/1 8593T SO8 plastic small outline package 8 leads body width 3.9 mm SOT96-1 3.1 Ordering options Table 2. Ordering options Type number Orderable Package Packing method Minimum Temperature part number order quantity PCF8593T/1 PCF8593T/1,118 SO8 REEL 13 Q1 NDP 2500 T = 40 C to +85 C amb 4. Block diagram V DD OSCI DIVIDER OSCILLATOR OSCO 00h control/status INT 01h hundredth second 02h seconds 03h minutes CONTROL RESET RESET LOGIC 04h hours 05h year/date PCF8593 06h weekdays/months 07h timer SCL 08h alarm control 2 I C-BUS ADDRESS to INTERFACE REGISTER alarm or RAM SDA 0Fh 013aaa379 V SS Fig 1. Block diagram of PCF8593 PCF8593 All information provided in this document is subject to legal disclaimers. NXP B.V. 2020. All rights reserved. Product data sheet Rev. 5 24 January 2020 2 of 31