PHU101NQ03LT,127 NXP

PHU101NQ03LT N-channel TrenchMOS logic level FET Rev. 04 30 June 2009 Product data sheet 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only. 1.2 Features and benefits Low conduction losses due to low Suitable for logic level gate drive on-state resistance sources Simple gate drive required due to low gate charge 1.3 Applications DC-to-DC convertors 1.4 Quick reference data Table 1. Quick reference Symbol Parameter Conditions Min Typ Max Unit V drain-source voltage T 25 C T 175 C - - 30 V DS j j I drain current T =25C V =10V --75 A D mb GS see Figure 1 see Figure 3 P total power T = 25 C see Figure 2 - - 166 W tot mb dissipation Dynamic characteristics Q gate-drain charge V =5V I =50A -8 -nC GD GS D V =15V T =25C DS j see Figure 11 Static characteristics R drain-source V =10V I =25A -4.5 5.5 m DSon GS D on-state resistance T = 25 C see Figure 9 j see Figure 10NXP Semiconductors PHU101NQ03LT N-channel TrenchMOS logic level FET 2. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline Graphic symbol 1G gate mb D 2D drain 3S source G mb D mounting base connected to drain mbb076 S 1 2 3 SOT533 (IPAK) 3. Ordering information Table 3. Ordering information Type number Package Name Description Version PHU101NQ03LT IPAK plastic single-ended package (IPAK) 3 leads (in-line) SOT533 PHU101NQ03LT 4 NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 30 June 2009 2 of 13