PMV117EN,215 NXP

PMV117EN TrenchMOS enhanced logic level FET Rev. 02 7 April 2005 Product data sheet 1. Product prole 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. 1.2 Features Logic level threshold Very fast switching Subminiature surface-mounted package 1.3 Applications Battery management Low power DC-to-DC converter High-speed switch 1.4 Quick reference data V 30 V I 2.5 A DS D R 117 m (V =10V) P 0.83 W DSon GS tot 2. Pinning information Table 1: Pinning Pin Description Simplied outline Symbol 1 gate (G) 3 D 2 source (S) 3 drain (D) G 12 mbb076 S SOT23PMV117EN Philips Semiconductors TrenchMOS enhanced logic level FET 3. Ordering information Table 2: Ordering information Type number Package Name Description Version PMV117EN TO-236AB plastic surface mounted package; 3 leads SOT23 4. Limiting values Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit V drain-source voltage (DC) 25 C T 150 C - 30 V DS j V drain-gate voltage (DC) 25 C T 150 C; R =20k -30 V DGR j GS V gate-source voltage (DC) - 20 V GS I drain current (DC) T =25 C; V =10V; Figure 2 and 3 - 2.5 A D sp GS T = 100 C; V =10V; Figure 2 - 1.6 A sp GS I peak drain current T =25 C; pulsed; t 10 s; Figure 3 -10 A DM sp p P total power dissipation T =25 C; Figure 1 - 0.83 W tot sp T storage temperature - 65 +150 C stg T junction temperature - 65 +150 C j Source-drain diode I source (diode forward) current (DC) T =25 C - 0.8 A S sp I peak source (diode forward) current T =25 C; pulsed; t 10 s - 3.3 A SM sp p 9397 750 14709 Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 02 7 April 2005 2 of 12