SPC5200CVR400B

Freescale Semiconductor Document Number: MPC5200BDS Rev. 4, 02/2010 Data Sheet: Technical Data MPC5200B Data Sheet TEPBGA272 27 mm x 27 mm Key features are shown below. Full duplex SPI mode MPC603e series e300 core IrDA mode from 2400 bps to 4 Mbps Superscalar architecture Fast Ethernet Controller (FEC) o o 760 MIPS at 400 MHz (40 C to +85 C) Supports 100Mbps IEEE 802.3 MII, 10 Mbps IEEE 16 KB Instruction cache, 16 KB Data cache 802.3 MII, 10 Mbps 7-wire interface Double precision FPU Universal Serial Bus Controller (USB) Instruction and Data MMU USB Revision 1.1 Host Standard and Critical interrupt capability Open Host Controller Interface (OHCI) SDRAM / DDR Memory Interface Integrated USB Hub, with two ports. 2 Up to 133 MHz operation Two Inter-Integrated Circuit Interfaces (I C) SDRAM and DDR SDRAM support Serial Peripheral Interface (SPI) 256 MB addressing range per CS, two CS available Dual CAN 2.0 A/B Controller (MSCAN) 32-bit data bus Implementation of version 2.0A/B CAN protocol Built-in initialization and refresh Standard and extended data frames Flexible multi-function External Bus Interface J1850 Byte Data Link Controller (BDLC) Supports interfacing to ROM/Flash/SRAM memories or J1850 Class B data communication network interface other memory mapped devices compatible and ISO compatible for low speed (<125 kbps) 8 programmable Chip Selects serial data communications in automotive applications. Non-multiplexed data access using 8-/16-/32-bit databus Supports 4X mode, 41.6 kbps with up to 26-bit address In-frame response (IFR) types 0, 1, 2, and 3 supported Short or Long Burst capable Systems level features Multiplexed data access using 8-/16-/32-bit databus Interrupt Controller supports four external interrupt with up to 25-bit address request lines and 47 internal interrupt sources Peripheral Component Interconnect (PCI) Controller GPIO/Timer functions Version 2.2 PCI compatibility Up to 56 total GPIO pins that support a variety of PCI initiator and target operation interrupt/WakeUp capabilities. 32-bit PCI Address/Data bus Eight GPIO pins with timer capability supporting input 33 and 66 MHz operation capture, output compare, and pulse width modulation PCI arbitration function (PWM) functions ATA Controller Real-time Clock with one-second resolution Version 4 ATA compatible external interfaceIDE Disk Systems Protection (watch dog timer, bus monitor) Drive connectivity Individual control of functional block clock sources BestComm DMA subsystem Power management: Nap, Doze, Sleep, Deep Sleep Intelligent virtual DMA Controller modes Dedicated DMA channels to control peripheral Support of WakeUp from low power modes by different reception and transmission sources (GPIO, RTC, CAN) Local memory (SRAM 16 KB) Test/Debug features 6 Programmable Serial Controllers (PSC) JTAG (IEEE 1149.1 test access port) UART or RS232 interface Common On-chip Processor (COP) debug port CODEC interface for Soft Modem, Master/Slave On-board PLL and clock generation 2 CODEC Mode, I S and AC97 Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Freescale Semiconductor, Inc., 2008, 2010. All rights reserved.Table of Contents 2 1 Electrical and Thermal Characteristics .4 1.3.14 I C 45 1.1 DC Electrical Characteristics .4 1.3.15 J1850 46 1.1.1 Absolute Maximum Ratings .4 1.3.16 PSC . 47 1.1.2 Recommended Operating Conditions .4 1.3.17 GPIOs and Timers 54 1.1.3 DC Electrical Specifications .5 1.3.18 IEEE 1149.1 (JTAG) AC Specifications 56 1.1.4 Electrostatic Discharge 7 2 Package Description . 57 1.1.5 Power Dissipation 7 2.1 Package Parameters 57 1.1.6 Thermal Characteristics 9 2.2 Mechanical Dimensions 58 1.2 Oscillator and PLL Electrical Characteristics 10 2.3 Pinout Listings . 59 1.2.1 System Oscillator Electrical Characteristics .11 3 System Design Information 64 1.2.2 RTC Oscillator Electrical Characteristics 11 3.1 Power Up/Down Sequencing 64 1.2.3 System PLL Electrical Characteristics 11 3.1.1 Power Up Sequence . 65 1.2.4 e300 Core PLL Electrical Characteristics .11 3.1.2 Power Down Sequence 65 1.3 AC Electrical Characteristics .12 3.2 System and CPU Core AVDD Power Supply Filtering. 65 1.3.1 AC Test Timing Conditions: 12 3.3 Pull-up/Pull-down Resistor Requirements 65 1.3.2 AC Operating Frequency Data 13 3.3.1 Pull-down Resistor Requirements for TEST pins65 1.3.3 Clock AC Specifications .13 3.3.2 Pull-up Requirements for the PCI Control Lines66 1.3.4 Resets 14 3.3.3 Pull-up/Pull-down Requirements for MEM MDQS 1.3.5 External Interrupts .15 Pins (SDRAM) . 66 1.3.6 SDRAM .17 3.3.4 .Pull-up/Pull-down Requirements for MEM MDQS 1.3.7 PCI .21 Pins (DDR 16-bit Mode) 66 1.3.8 Local Plus Bus 23 3.4 JTAG 66 1.3.9 ATA .28 3.4.1 JTAG TRST . 66 1.3.10 Ethernet .38 3.4.2 e300 COP/BDM Interface 67 1.3.11 USB 40 4 Ordering Information . 69 1.3.12 SPI .41 5 Document Revision History 70 1.3.13 MSCAN .45 MPC5200B Data Sheet, Rev. 4 2 Freescale Semiconductor