ST72F651AR6T1E

ST72651AR6 Low-power, full-speed USB 8-bit MCU with 32 KB Flash, 5 KB 2 RAM, Flash card interface, timer, PWM, ADC, I C, SPI Memories Up to 32 KB of High Density Flash (HDFlash) program memory with read/write protection For HDFlash devices, In-Application Pro- gramming (IAP) via USB and In-Circuit pro- gramming (ICP) LQFP64 10x10 Up to 5 KB of RAM with up to 256 B stack Clock, Reset and Supply Management Mass Storage Interface PLL for generating 48 MHz USB clock using a DTC (Data Transfer Coprocessor): Universal 12 MHz crystal Serial/Parallel communications interface, with software plug-ins for current and future proto- Low Voltage Reset (except on E suffix devic- col standards: es) Compact Flash - Multimedia Card - Dual supply management: analog voltage de- Secure Digital Card - SmartMediaCard - tector on the USB power line to enable smart power switching from USB power to battery Sony Memory Stick - NAND Flash - (on E suffix devices). ATA Peripherals Programmable Internal Voltage Regulator for 2 Timers Memory cards (2.8V to 3.5V) supplying: Flash Card I/O lines (voltage shifting) Configurable Watchdog for system reliability Up to 50 mA for Flash card supply 16-bit Timer with 2 output compare functions. Clock-out capability 2 Communication Interfaces 47 programmable I/O lines SPI synchronous serial interface 2 15 high sink I/Os (8mA 0.6V / 20mA 1.3V) I C Single Master Interface up to 400 KHz 5 true open drain outputs D/A and A/D Peripherals 24 lines programmable as interrupt inputs PWM/BRM Generator (with 2 10-bit PWM/ USB (Universal Serial Bus) Interface BRM outputs) 8-bit A/D Converter (ADC) with 8 channels with DMA for full speed bulk applications com- pliant with USB 12 Mbs specification (version Instruction Set 2.0 compliant) 8-bit data manipulation On-Chip 3.3V USB voltage regulator and 63 basic instructions transceivers with software power-down 17 main addressing modes 5 USB endpoints: 1 control endpoint 8 x 8 unsigned multiply instruction 2 IN endpoints supporting interrupt and bulk True bit manipulation 2 OUT endpoints supporting interrupt and Development Tools bulk Hardware conversion between USB bulk Full hardware/software development package packets and 512-byte blocks Device Summary Features ST72651AR6 Program memory 32 Kbytes of Flash program memory User RAM (stack) - bytes 5 Kbyte (256) 2 Peripherals USB, DTC, Timer, ADC, SPI, I C, PWM, WDT Operating Supply 4.0 to 5.5 V (for USB) Dual 3.0 to 5.5 V or 4.0 to 5.5 V (for USB) Package LQFP64 (10 x10) Operating Temperature 0 to +70 C June 2009 1/161 Doc ID 7215 Rev 4 1Table of Contents 1 INTRODUCTION 4 2 PIN DESCRIPTION 7 3 REGISTER & MEMORY MAP . 16 4 FLASH PROGRAM MEMORY 20 4.1 INTRODUCTION 20 4.2 MAIN FEATURES . 20 4.3 STRUCTURE . 20 4.4 READ-OUT PROTECTION 20 4.5 ICC INTERFACE 21 4.6 ICP (IN-CIRCUIT PROGRAMMING) . 22 4.7 IAP (IN-APPLICATION PROGRAMMING) . 22 4.8 RELATED DOCUMENTATION . 22 4.9 REGISTER DESCRIPTION 22 5 CENTRAL PROCESSING UNIT . 23 5.1 INTRODUCTION 23 5.2 MAIN FEATURES . 23 5.3 CPU REGISTERS . 23 6 SUPPLY, RESET AND CLOCK MANAGEMENT 26 6.1 CLOCK SYSTEM 26 6.2 RESET SEQUENCE MANAGER (RSM) 27 6.3 LOW VOLTAGE DETECTOR (LVD) . 30 6.4 POWER SUPPLY MANAGEMENT 31 7 INTERRUPTS . 37 7.1 INTRODUCTION 37 7.2 MASKING AND PROCESSING FLOW . 37 7.3 INTERRUPTS AND LOW POWER MODES . 39 7.4 CONCURRENT & NESTED MANAGEMENT 39 7.5 INTERRUPT REGISTER DESCRIPTION . 40 8 POWER SAVING MODES . 43 8.1 INTRODUCTION 43 8.2 WAIT MODE . 43 8.3 HALT MODE . 44 9 I/O PORTS 45 9.1 INTRODUCTION 45 9.2 FUNCTIONAL DESCRIPTION 45 9.3 I/O PORT IMPLEMENTATION 49 9.4 REGISTER DESCRIPTION 50 10 MISCELLANEOUS REGISTERS . 52 11 ON-CHIP PERIPHERALS . 54 11.1 WATCHDOG TIMER (WDG) . 54 11.2 DATA TRANSFER COPROCESSOR (DTC) . 57 11.3 USB INTERFACE (USB) 61 2/161 Doc ID 7215 Rev 4 1 -