ST72F321J7T6

ST72321Rx ST72321ARx ST72321Jx 64/44-pin 8-bit MCU with 32 to 60K Flash/ROM, ADC, 2 five timers, SPI, SCI, I C interface Features Memories 32K to 60K dual voltage High Density Flash (HDFlash) or ROM with read-out protection capability. In-Application Programming and In-Circuit Programming for HDFlash devices LQFP64 LQFP32 1K to 2K RAM 14 x 14 7 x 7 HDFlash endurance: 100 cycles, data reten- tion: 40 years at 85C Clock, Reset And Supply Management Enhanced low voltage supervisor (LVD) for main supply and auxiliar voltage detector (AVD) with interrupt capability Clock sources: crystal/ceramic resonator os- LQFP64 LQFP44 cillators, internal RC oscillator and bypass for 10 x 10 10 x 10 external clock PLL for 2x frequency multiplication 8-bit PWM Auto-reload timer with: 2 input cap- Four Power Saving Modes: Halt, Active-Halt, tures, 4 PWM outputs, output compare and Wait and Slow time base interrupt, external clock with event Interrupt Management detector 3 Communications Interfaces Nested interrupt controller 14 interrupt vectors plus TRAP and RESET SPI synchronous serial interface Top Level Interrupt (TLI) pin on 64-pin devices SCI asynchronous serial interface 2 15/9 external interrupt lines (on 4 vectors) I C multimaster interface Up to 48 I/O Ports 1 Analog peripheral 48/32/24 multifunctional bidirectional I/O lines 10-bit ADC with up to 16 input ports 34/22/17 alternate function lines Instruction Set 16/12/10 high sink outputs 8-bit Data Manipulation 5 Timers 63 Basic Instructions Main Clock Controller with: Real time base, 17 main Addressing Modes Beep and Clock-out capabilities 8 x 8 Unsigned Multiply Instruction Configurable watchdog timer Development Tools Two 16-bit timers with: 2 input captures, 2 out- Full hardware/software development package put compares, external clock input on one tim- er, PWM and pulse generator modes In-Circuit Testing capability Table 1. Device summary ST72321R9/ST72321AR9/ ST72321R7/ST72321AR7/ Features ST72321R6/ST72321AR6 ST72321J9 ST72321J7 Program memory - bytes Flash/ROM 60K Flash/ROM 48K Flash/ROM 32K RAM (stack) - bytes 2048 (256) 1536 (256) 1024 (256) Operating Voltage 3.8 to 5.5V Temp. Range -40 to +125C, -40 to +85C Package LQFP64 14x14 (R), LQFP64 10x10 (AR), LQFP44 10x10 (J) March 2009 Rev 2 1/193 1Table of Contents 1 DESCRIPTION . 7 2 PIN DESCRIPTION 8 3 REGISTER & MEMORY MAP . 14 4 FLASH PROGRAM MEMORY 18 4.1 INTRODUCTION 18 4.2 MAIN FEATURES . 18 4.3 STRUCTURE . 18 4.3.1 Read-out Protection 18 4.4 ICC INTERFACE 19 4.5 ICP (IN-CIRCUIT PROGRAMMING) . 20 4.6 IAP (IN-APPLICATION PROGRAMMING) . 20 4.7 RELATED DOCUMENTATION . 20 4.7.1 Register Description . 20 5 CENTRAL PROCESSING UNIT . 21 5.1 INTRODUCTION 21 5.2 MAIN FEATURES . 21 5.3 CPU REGISTERS . 21 6 SUPPLY, RESET AND CLOCK MANAGEMENT 24 6.1 PHASE LOCKED LOOP 24 6.2 MULTI-OSCILLATOR (MO) 25 6.3 RESET SEQUENCE MANAGER (RSM) 26 6.3.1 Introduction 26 6.3.2 Asynchronous External RESET pin 26 6.3.3 External Power-On RESET 27 6.3.4 Internal Low Voltage Detector (LVD) RESET 27 6.3.5 Internal Watchdog RESET 27 6.4 SYSTEM INTEGRITY MANAGEMENT (SI) 28 6.4.1 Low Voltage Detector (LVD) . 28 6.4.2 Auxiliary Voltage Detector (AVD) . 29 6.4.3 Low Power Modes 30 6.4.4 Register Description . 31 7 INTERRUPTS . 32 7.1 INTRODUCTION 32 7.2 MASKING AND PROCESSING FLOW . 32 7.3 INTERRUPTS AND LOW POWER MODES . 34 7.4 CONCURRENT & NESTED MANAGEMENT 34 7.5 INTERRUPT REGISTER DESCRIPTION . 35 7.6 EXTERNAL INTERRUPTS 37 7.6.1 I/O Port Interrupt Sensitivity 37 7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) . 39 8 POWER SAVING MODES . 41 8.1 INTRODUCTION 41 193 8.2 SLOW MODE . 41 8.3 WAIT MODE . 42 2/193 1