74AC245, 74ACT245 Octal Bidirectional Transceiver with 3-STATE Inputs/Outputs January 2008 74AC245, 74ACT245 Octal Bidirectional Transceiver with 3-STATE Inputs/Outputs Features General Description I and I reduced by 50% The AC/ACT245 contains eight non-inverting bidirec- CC OZ tional buffers with 3-STATE outputs and is intended for Non-inverting buffers bus-oriented applications. Current sinking capability is Bidirectional data path 24mA at both the A and B ports. The Transmit/Receive A and B outputs source/sink 24mA (T/R ) input determines the direction of data flow through ACT245 has TTL-compatible inputs the bidirectional transceiver. Transmit (active-HIGH) enables data from A ports to B ports Receive (active- LOW) enables data from B ports to A ports. The Output Enable input, when HIGH, disables both A and B ports by placing them in a HIGH Z condition. Ordering Information Package Order Number Number Package Description 74AC245SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74AC245SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74AC245MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74AC245PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 74ACT245SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74ACT245SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACT245MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 74ACT245MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACT245PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. 1988 Fairchild Semiconductor Corporation www.fairchildsemi.com 74AC245, 74ACT245 Rev. 1.5.074AC245, 74ACT245 Octal Bidirectional Transceiver with 3-STATE Inputs/Outputs Connection Diagram Logic Symbol IEEE/IEC Pin Description Pin Names Description OE Output Enable Input T/R Transmit/Receive Input A A Side A 3-STATE Inputs or 3-STATE 0 7 Outputs B B Side B 3-STATE Inputs or 3-STATE 0 7 Outputs Truth Table Inputs OE T/R Outputs LL Bus B Data to Bus A LH Bus A Data to Bus B HX HIGH-Z State H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial 1988 Fairchild Semiconductor Corporation www.fairchildsemi.com 74AC245, 74ACT245 Rev. 1.5.0 2