CAT24C64 2 64 Kb I C CMOS Serial EEPROM Description The CAT24C64 is a 64 Kb CMOS Serial EEPROM device, internally organized as 8192 words of 8 bits each. www.onsemi.com It features a 32byte page write buffer and supports the Standard 2 (100 kHz), Fast (400 kHz) and FastPlus (1 MHz) I C protocol. External address pins make it possible to address up to eight CAT24C64 devices on the same bus. SOIC8 TSSOP8 Features W SUFFIX Y SUFFIX 2 Supports Standard, Fast and FastPlus I C Protocol CASE 751BD CASE 948AL 1.7 V to 5.5 V Supply Voltage Range 32Byte Page Write Buffer UDFN8 WLCSP4 WLCSP4 Hardware Write Protection for Entire Memory HU4 SUFFIX C4C SUFFIX C4U SUFFIX 2 CASE 517AZ CASE 567JY CASE 567PB Schmitt Triggers and Noise Suppression Filters on I C Bus Inputs (SCL and SDA) Low Power CMOS Technology PIN CONFIGURATIONS (Top Views) 1,000,000 Program/Erase Cycles 1 1 V A CC 0 100 Year Data Retention V A1 A2 V CC SS WP A 1 Industrial and Extended Temperature Range A SCL 2 SCL B1 B2 SDA SOIC, TSSOP, UDFN 8pad and Ultrathin WLCSP 4bump V SDA SS Packages SOIC (W), TSSOP (Y), WLCSP UDFN (HU4) This Device is PbFree, Halogen Free/BFR Free, and RoHS (C4C) (C4U) Compliant MARKING X X DIAGRAMS V CC YM YW (WLCSP4) X = Specific Device Code = (see ordering information) SCL Y = Production Year (Last Digit) M = Production Month (19, O, N, D) W = Production Week Code CAT24C64 SDA A , A , A 2 1 0 For the location of Pin 1, please consult the corresponding package drawing. WP PIN FUNCTION Pin Name Function V SS A , A , A Device Address 0 1 2 SDA Serial Data Figure 1. Functional Symbol SCL Serial Clock WP Write Protect V Power Supply CC V Ground SS ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet. For serial EEPROM in a US8 package, please consult the N24C64 datasheet. Semiconductor Components Industries, LLC, 2018 1 Publication Order Number: April, 2018 Rev. 27 CAT24C64/DCAT24C64 Table 1. ABSOLUTE MAXIMUM RATINGS Parameters Ratings Units Storage Temperature 65 to +150 C Voltage on Any Pin with Respect to Ground (Note 1) 0.5 to +6.5 V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. The DC input voltage on any pin should not be lower than 0.5 V or higher than V + 0.5 V. During transitions, the voltage on any pin may CC undershoot to no less than 1.5 V or overshoot to no more than V + 1.5 V, for periods of less than 20 ns. CC Table 2. RELIABILITY CHARACTERISTICS (Note 2) Symbol Parameter Min Units N (Note 3) Endurance 1,000,000 Program/Erase Cycles END T Data Retention 100 Years DR 2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AECQ100 and JEDEC test methods. 3. Page Mode, V = 5 V, 25C. CC Table 3. D.C. OPERATING CHARACTERISTICS (V = 1.8 V to 5.5 V, T = 40C to +125C and V = 1.7 V to 5.5 V, T = 40C to +85C, unless otherwise specied.) CC A CC A Symbol Parameter Test Conditions Min Max Units I Read Current Read, f = 400 kHz 1 mA CCR SCL I Write Current Write, f = 400 kHz 2 mA CCW SCL I Standby Current All I/O Pins at GND or V T = 40C to +85C 1 A SB CC A V 3.3 V CC T = 40C to +85C 3 A V > 3.3 V CC T = 40C to +125C 5 A I I/O Pin Leakage Pin at GND or V 2 A L CC V Input Low Voltage 0.5 V x 0.3 V IL CC V Input High Voltage V x 0.7 V + 0.5 V IH CC CC V Output Low Voltage V 2.5 V, I = 3.0 mA 0.4 V OL1 CC OL V Output Low Voltage V < 2.5 V, I = 1.0 mA 0.2 V OL2 CC OL Table 4. PIN IMPEDANCE CHARACTERISTICS (V = 1.8 V to 5.5 V, T = 40C to +125C and V = 1.7 V to 5.5 V, T = 40C to +85C, unless otherwise specied.) CC A CC A Symbol Parameter Conditions Max Units C (Note 4) SDA I/O Pin Capacitance V = 0 V 8 pF IN IN C (Note 4) Input Capacitance (other pins) V = 0 V 6 pF IN IN I (Note 5) WP Input Current V < V , V = 5.5 V 130 A WP IN IH CC V < V , V = 3.3 V 120 IN IH CC V < V , V = 1.8 V 80 IN IH CC V > V 2 IN IH I (Note 5) Address Input Current V < V , V = 5.5 V 50 A A IN IH CC (A0, A1, A2) V < V , V = 3.3 V 35 IN IH CC Product Rev F V < V , V = 1.8 V 25 IN IH CC V > V 2 IN IH 4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AECQ100 and JEDEC test methods. 5. When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pulldown is relatively strong therefore the external driver must be able to supply the pulldown current when attempting to drive the input HIGH. To conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V ), the strong pulldown reverts to a weak current source. CC www.onsemi.com 2