CAT28F512 Licensed Intel 512K-Bit CMOS Flash Memory second source FEATURES Commercial, Industrial and Automotive Fast Read Access Time: 90/120/150 ns Temperature Ranges Low Power CMOS Dissipation: Active: 30 mA max (CMOS/TTL levels) Stop Timer for Program/Erase Standby: 1 mA max (TTL levels) On-Chip Address and Data Latches Standby: 100 A max (CMOS levels) JEDEC Standard Pinouts: High Speed Programming: 32-pin DIP 10 s per byte 32-pin PLCC 1 Sec Typ Chip Program 32-pin TSOP ( 8 x 20) 12.0V 5% Programming and Erase Voltage 100,000 Program/Erase Cycles Electronic Signature 10 Year Data Retention Gree Package Options Available DESCRIPTION two write cycle scheme. Address and Data are latched The CAT28F512 is a high speed 64K x 8-bit electrically to free the I/O bus and address bus during the write erasable and reprogrammable Flash memory ideally operation. suited for applications requiring in-system or after-sale code updates. Electrical erasure of the full memory The CAT28F512 is manufactured using Catalysts ad- contents is achieved typically within 0.5 second. vanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data It is pin and Read timing compatible with standard retention of 10 years. The device is available in JEDEC EPROM and EEPROM devices. Programming and Erase approved 32-pin plastic DIP, 32-pin PLCC or 32-pin are performed through an operation and verify algo- TSOP packages. rithm. The instructions are input via the I/O bus, using a BLOCK DIAGRAM I/O I/O 0 7 I/O BUFFERS ERASE VOLTAGE SWITCH WE DATA SENSE COMMAND PROGRAM VOLTAGE CE, OE LOGIC LATCH AMP REGISTER SWITCH CE OE Y-GATING Y-DECODER 524,288 BIT A A 0 15 MEMORY X-DECODER ARRAY VOLTAGE VERIFY SWITCH 2009 SCILLC. All rights reserved. Doc. No. MD-1084, Rev. K Characteristics subject to change without notice 1 ADDRESS LATCHCAT28F512 PIN CONFIGURATION PIN FUNCTIONS Pin Name Type Function A A Input Address Inputs for 0 15 memory addressing DIP Package (L) PLCC Package (N, G) I/O I/O I/O Data Input/Output 0 7 CE Input Chip Enable V 1 32 V PP CC NC 2 31 WE 4321 323130 OE Input Output Enable A 3 30 N/C 15 5 29 A A 7 14 A 4 29 A 12 14 6 28 A A 6 13 A 5 28 A WE Input Write Enable 7 13 7 27 A A 5 8 A 6 27 A 6 8 8 26 A A 4 9 A 7 26 A 5 9 V Voltage Supply CC 9 25 A A 3 11 A 8 25 A 4 11 10 24 A OE 2 A 9 24 OE 3 11 23 V Ground A A SS 1 10 A 10 23 A 2 10 12 22 A CE 0 A 11 22 CE 1 13 21 I/O I/O 0 7 V Program/Erase PP A 12 21 I/O 14 15 16 17 18 19 20 0 7 Voltage Supply I/O 13 20 I/O 0 6 I/O 14 19 I/O 1 5 I/O 15 18 I/O 2 4 V 16 17 I/O SS 3 28F512 F01 TSOP Package (Standard Pinout 8mm x 20mm) (T, H) A 1 32 OE 11 A 2 31 A 9 10 A 3 30 CE 8 A 4 29 I/O 13 7 A 5 28 I/O 14 6 NC 6 27 I/O 5 WE 7 26 I/O 4 V 8 25 I/O CC 3 V 9 24 V PP SS 10 23 I/O NC 2 A 11 22 I/O 15 1 A 12 21 I/O 12 0 A 13 20 A 7 0 A 14 19 A 6 1 A 15 18 A 5 2 A 16 17 A 4 3 TSOP Package (Reverse Pinout) (TR, HR) OE 1 32 A 11 A 2 31 A 10 9 CE 3 30 A 8 I/O 4 29 A 7 13 I/O 5 28 A 6 14 I/O 6 27 NC 5 I/O 7 26 WE 4 I/O 8 25 V 3 CC 9 24 V V SS PP 10 23 NC I/O 2 11 22 A I/O 1 15 12 21 I/O A 12 0 13 20 A A 7 0 14 19 A A 6 1 15 18 A A 5 2 16 17 A A 3 4 28F512 F03 2009 SCILLC. All rights reserved. Doc. No. MD-1084, Rev. K 2 Characteristics subject to change without notice I/O A 1 12 I/O A 2 15 V NC SS I/O V 3 PP I/O V 4 CC I/O WE 5 I/O N/C 6