Single 1 A High-Speed, Low-Side Gate Driver FAN3111C, FAN3111E Description The FAN3111 1 A gate driver is designed to drive an Nchannel enhancementmode MOSFET in lowside switching applications. www.onsemi.com Two input options are offered: FAN3111C has dual CMOS inputs with thresholds referenced to V for use with PWM controllers and DD other inputsignal sources that operate from the same supply voltage as the driver. For use with low voltage controllers and other inputsignal sources that operate from a lower supply voltage than the SOT235 driver, that supply voltage may also be used as the reference for the CASE 527AH input thresholds of the FAN3111E. This driver has a single, noninverting, lowvoltage input plus a DC input V for an XREF PIN ASSIGNMENT external reference voltage in the range 2 to 5 V. The FAN3111 is available in a leadfree finish industrystandard 5pin SOT23. VDD 1 5 OUT Features 2 GND 1.4 A Peak Sink/Source at V = 12 V DD IN+ 3 4 IN 1.1 A Sink/0.9 A Source at V = 6 V OUT 4.5 to 18 V Operating Range FAN3111C (Top View) FAN3111C Compatible with FAN3100C Footprint Two Input Configurations: 1 VDD 5 OUT Dual CMOS Inputs Allow Configuration as NonInverting or Inverting with Enable Function GND 2 Single NonInverting, LowVoltage Input for 3 IN+ 4 XREF Compatibility with LowVoltage Controllers Small Footprint Facilitates Distributed Drivers for FAN3111E (Top View) Parallel Power Devices 15 ns Typical Delay Times MARKING DIAGRAM 9 ns Typical Rise/8 ns Typical Fall times with 470 pF Load 5Pin SOT23 Package Rated from 40C to 125C Ambient &E&E&Y &O111X&C These Devices are PbFree and Halogen Free &.&O&E&V Applications SwitchMode Power Supplies Synchronous Rectifier Circuits &E = Designates Space Pulse Transformer Driver &Y = Binary Calendar Year Coding Scheme &O = Plant Code identifier Logic to Power Buffer 111X = Device Specific Code Motor Control X = C or E &C = Single digit Die Run Code &. = Pin One Dot &V = EightWeek Binary Datecoding Scheme ORDERING INFORMATION See detailed ordering and shipping information on page 16 of this data sheet. Semiconductor Components Industries, LLC, 2008 1 Publication Order Number: June, 2021 Rev. 3 FAN3111C/DFAN3111C, FAN3111E THERMAL CHARACTERISTICS (Note 1) JL JT JA JB JT Package (Note 2) (Note 3) (Note 4) (Note 5) (Note 6) Unit 5Pin SOT23 58 102 161 53 6 C/W 1. Estimates derived from thermal simulation actual values depend on the application. 2. Theta JL ( ): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any thermal pad) JL that are typically soldered to a PCB. 3. Theta JT ( ): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is held at a uniform JT temperature by a top side heatsink. 4. Theta JA ( ): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow. The value given JA is for natural convection with no heatsink using a 2S2P board, as specified in JEDEC standards JESD512, JESD515, and JESD517, as appropriate. 5. Psi JB ( ): Thermal characterization parameter providing correlation between semiconductor junction temperature and an application JB circuit board reference point for the thermal environment defined in Note 4. For the MLP8 package, the board reference is defined as the PCB copper connected to the thermal pad and protruding from either end of the package. For the SOIC8 package, the board reference is defined as the PCB copper adjacent to pin 6. 6. Psi JT ( ): Thermal characterization parameter providing correlation between the semiconductor junction temperature and the center of JT the top of the package for the thermal environment defined in Note 4. PIN DEFINITIONS Pin Number Name Description 1 VDD Supply Voltage. Provides power to the IC. 2 GND Ground. Common ground reference for input and output circuits. 3 IN+ NonInverting Input. Connect to VDD to enable output. IN FAN3111C Inverting Input. Connect to GND to enable output. 4 XREF FAN3111E External Reference Voltage. Reference for input thresholds, 2 V to 5 V. 5 OUT Gate Drive Output. Held low unless required inputs are present. OUTPUT LOGIC WITH DUALINPUT CONFIGURATION IN+ IN OUT 0 (Note 7) 0 0 0 (Note 7) 1 (Note 7) 0 1 0 1 1 1 (Note 7) 0 7. Default input signal if no external connection is made. www.onsemi.com 2