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Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. FDMS3600S PowerTrench Power Stage August 2011 FDMS3600S PowerTrench Power Stage 25 V Asymmetric Dual N-Channel MOSFET Features General Description Q1: N-Channel This device includes two specialized N-Channel MOSFETs in a dual PQFN package. The switch node has been internally Max r = 5.6 m at V = 10 V, I = 15 A DS(on) GS D connected to enable easy placement and routing of synchronous Max r = 8.1 m at V = 4.5 V, I = 14 A DS(on) GS D buck converters. The control MOSFET (Q1) and synchronous Q2: N-Channel SyncFET (Q2) have been designed to provide optimal power Max r = 1.6 m at V = 10 V, I = 30 A DS(on) GS D efficiency. Max r = 2.4 m at V = 4.5 V, I = 25 A DS(on) GS D Applications Low inductance packaging shortens rise/fall times, resulting in lower switching losses Computing MOSFET integration enables optimum layout for lower circuit Communications inductance and reduced switch node ringing General Purpose Point of Load RoHS Compliant Notebook VCORE Server G1 Pin 1 D1 D1 D1 Q 2 D1 S2 D1 5 4 PHASE PHASE S2 6 3 D1 (S1/D2) D1 S2 7 2 G2 S2 G2 S2 G1 8 1 Q 1 S2 Top Bottom Power 56 MOSFET Maximum Ratings T = 25 C unless otherwise noted A Symbol Parameter Q1 Q2 Units V Drain to Source Voltage 25 25 V DS V Gate to Source Voltage (Note 3) 20 20 V GS Drain Current -Continuous (Package limited) T = 25 C 30 40 C -Continuous (Silicon limited) T = 25 C 65 155 C I A D 1a 1b -Continuous T = 25 C 15 30 A -Pulsed 40 100 4 5 E Single Pulse Avalanche Energy 50 200 mJ AS 1a 1b Power Dissipation for Single Operation T = 25 C 2.2 2.5 A P W D 1c 1d Power Dissipation for Single Operation T = 25 C 1.0 1.0 A T , T Operating and Storage Junction Temperature Range -55 to +150 C J STG Thermal Characteristics 1a 1b R Thermal Resistance, Junction to Ambient 57 50 JA 1c 1d R Thermal Resistance, Junction to Ambient 125 120 C/W JA R Thermal Resistance, Junction to Case 3.5 2 JC Package Marking and Ordering Information Device Marking Device Package Reel Size Tape Width Quantity 22OA FDMS3600S Power 56 13 12 mm 3000 units N9OC 1 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMS3600S Rev.C3