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FDMS3624S PowerTrench Power Stage December 2011 FDMS3624S PowerTrench Power Stage 25V Asymmetric Dual N-Channel MOSFET Features General Description Q1: N-Channel This device includes two specialized N-Channel MOSFETs in a Max r = 5.0 m at V = 10 V, I = 17.5 A DS(on) GS D dual PQFN package. The switch node has been internally Max r = 5.7 m at V = 4.5 V, I = 16 A connected to enable easy placement and routing of synchronous DS(on) GS D buck converters. The control MOSFET (Q1) and synchronous Q2: N-Channel SyncFET (Q2) have been designed to provide optimal power Max r = 1.8 m at V = 10 V, I = 30 A DS(on) GS D efficiency. Max r = 2.2 m at V = 4.5 V, I = 27 A DS(on) GS D Low inductance packaging shortens rise/fall times, resulting in Applications lower switching losses Computing MOSFET integration enables optimum layout for lower circuit Communications inductance and reduced switch node ringing General Purpose Point of Load RoHS Compliant Notebook VCORE G1 Pin 1 D1 D1 D1 D1 Pin 1 PHASE (S1/D2) G2 S2 S2 S2 Top Bottom Power 56 MOSFET Maximum Ratings T = 25 C unless otherwise noted A Symbol Parameter Q1 Q2 Units V Drain to Source Voltage 25 25 V DS V Gate to Source Voltage (Note 4) 12 12 V GS Drain Current -Continuous (Package limited) T = 25 C 30 60 C 1a 1b I -Continuous T = 25 C 17.5 30 A D A -Pulsed 70 120 E Single Pulse Avalanche Energy (Note 3) 29 86 mJ AS 1a 1b Power Dissipation for Single Operation T = 25 C 2.2 2.5 A P W D 1c 1d Power Dissipation for Single Operation T = 25 C 1.0 1.0 A T , T Operating and Storage Junction Temperature Range -55 to +150 C J STG Thermal Characteristics 1a 1b R Thermal Resistance, Junction to Ambient 57 50 JA 1c 1d R Thermal Resistance, Junction to Ambient 125 120 C/W JA R Thermal Resistance, Junction to Case 3.0 2.2 JC Package Marking and Ordering Information Device Marking Device Package Reel Size Tape Width Quantity 08OD FDMS3624S Power 56 13 12 mm 3000 units 07OD 2011 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com FDMS3624S Rev.C2