DATA SHEET www.onsemi.com High-Speed 10 MBit/s Logic Gate Optocouplers PDIP8 6.6x3.81, 2.54P CASE 646BW 8 1 Single-Channel: 6N137, HCPL2601, HCPL2611 Dual-Channel: HCPL2630, PDIP8 9.655x6.6, 2.54P CASE 646CQ 8 HCPL2631 1 Description The 6N137, HCPL2601, HCPL2611 single channel and PDIP8 GW HCPL2630, HCPL2631 dualchannel optocouplers consist of a CASE 709AC 8 850nm AlGaAS LED, optically coupled to a very high speed integrated photodetector logic gate with a strobable output. This 1 output features an open collector, thereby permitting wired OR outputs. The coupled parameters are guaranteed over the temperature MARKING DIAGRAM range of 40C to +85C. A maximum input signal of 5 mA will provide a minimum output sink current of 13 mA (fan out of 8). ON An internal noise shield provides superior common mode rejection 2601 of typically 10 kV/ s. The HCPL2601 and HCPL2631 has a minimum VXXYYT1 CMR of 5 kV/ s. The HCPL2611 has a minimum CMR of 10 kV/ s. 2601 = Device Number Features V = VDE mark (Note: Only Appears on Very High Speed 10 MBit/s Parts Ordered with VDE Option See Order Entry Table) Superior CMR 10 kV/ s XX = TwoDigit Year Code, e.g., 03 Double working voltage 480 V YY = TwoDigit Work Week, Ranging from Fanout of 8 Over 40C to +85C 01 to 53 T1 = Assembly Package Code Logic Gate Output Strobable Output ORDERING INFORMATION Wired ORopen Collector See detailed ordering and shipping information on page 10 of U.L. Recognized (File E90700) this data sheet. Applications Ground Loop Elimination LSTTL to TTL, LSTTL or 5volt CMOS Line Receiver, Data Transmission Data Multiplexing Switching Power Supplies Pulse Transformer Replacement Computerperipheral Interface Semiconductor Components Industries, LLC, 2005 1 Publication Order Number: August, 2021 Rev. 3 HCPL2631/DSingleChannel: 6N137, HCPL2601, HCPL2611 Dual Channel: HCPL2630, HCPL2631 SCHEMATICS V N/C 1 8 + 1 8 V CC CC V F1 V + 2 7 2 7 V E 01 V F V 3 6 3 6 V O 02 V F2 + N/C 4 5 GND 4 5 GND 6N137, HCPL2601, HCPL2630, HCPL2611 HCPL2631 A 0.1 F bypass capacitor must be connected between pins 8 and 5 (Note 1). Figure 1. Schematics TRUTH TABLE (Positive Logic) Input Enable Output H H L L H H H L H L L H H NC L L NC H www.onsemi.com 2