MC10E016, MC100E016 5.0 V ECL 8Bit Synchronous Binary Up Counter Description www.onsemi.com The MC10E/100E016 is a high-speed synchronous, presettable, cascadable 8-bit binary counter. Architecture and operation are the same as the MC10H016 in the MECL 10H family, extended to 8-bits, as shown in the logic symbol. The counter features internal feedback of TC, gated by the TCLD (terminal count load) pin. When TCLD is LOW (or left open, in which case it is pulled LOW by the internal pull-downs), the TC feedback is PLCC28 disabled, and counting proceeds continuously, with TC going LOW to FN SUFFIX indicate an all-one state. When TCLD is HIGH, the TC feedback CASE 77602 causes the counter to automatically reload upon TC = LOW, thus functioning as a programmable counter. The Q outputs do not need to n be terminated for the count function to operate properly. To minimize noise and power, unused Q outputs should be left unterminated. MARKING DIAGRAM* The 100 series contains temperature compensation. 1 Features 700 MHz Min. Count Frequency MCxxxE016G 1000 ps CLK to Q, TC AWLYYWW Internal TC Feedback (Gated) 8-Bit xxx = 10 or 100 Fully Synchronous Counting and TC Generation A = Assembly Location Asynchronous Master Reset WL = Wafer Lot YY = Year PECL Mode Operating Range: V = 4.2 V to 5.7 V CC WW = Work Week with V = 0 V EE G = Pb-Free Package NECL Mode Operating Range: V = 0 V CC *For additional marking information, refer to with V = 4.2 V to 5.7 V EE Application Note AND8002/D. These Devices are Pb-Free, Halogen Free and are RoHS Compliant ORDERING INFORMATION Device Package Shipping MC10E016FNG PLCC28 37 Units/Tube (Pb-Free) MC10E016FNR2G PLCC28 500 Tape & Reel (Pb-Free) 37 Units/Tube MC100E016FNG PLCC28 (Pb-Free) MC100E016FNR2G PLCC28 500 Tape & Reel (Pb-Free) For information on tape and reel specifications, in- cluding part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: July, 2016 Rev. 8 MC10E016/DMC10E016, MC100E016 PE CE P P P V TC 7 6 5 CCO Table 1. PIN DESCRIPTION PIN FUNCTION 25 24 23 22 21 20 1 18 Q MR 26 9 7 P0 P ECL Parallel Data (Preset) Inputs 7 Q Q ECL Data Outputs CLK 27 17 Q 6 0 7 CE ECL Count Enable Control Input TCLD 28 16 V CC PE ECL Parallel Load Enable Control Input 1 MR ECL Master Reset V 15 Q EE 5 CLK ECL Clock NC 2 14 V TC ECL Terminal Count Output CCO TCLD ECL TCLoad Control Input P 3 13 Q 0 4 NC No Connect V , V Positive Supply P 4 1 12 Q CC CCO 3 V Negative Supply EE 56 7 8 9 10 11 P P P V Q Q Q 2 3 4 CCO 0 1 2 All V and V pins are tied together on the die. CC CCO Warning: All V , V , and V pins must be externally CC CCO EE connected to Power Supply to guarantee proper operation. Figure 1. 28-Lead Pinout Assignment (Top View) Q Q Q 1 7 0 PE TCLD Q0M CE Q 0 Q 1 Q CE 2 MASTER SLAVE BIT 1 BIT 7 CE Q0M Q 0 Q 3 Q BIT 0 4 Q 5 Q 6 PO P 1 P7 MR CLK BITS 2-6 TC Note that this diagram is provided for understanding of 5 logic operation only. It should not be used for propagation delays as many gate functions are achieved internally without incurring a full gate delay. Figure 2. 8-Bit Binary Counter Logic Counter Table 2. FUNCTION TABLE FUNCTION CE PE TCLD MR CLK Load Parallel (P to Q ) X L X L Z n n Continuous Count L H L L Z Count Load Parallel on TC = LOW L H H L Z Hold H H X L Z Masters Respond, Slaves Hold X X X L ZZ Reset (Q : = LOW, TC : = HIGH) X X X H X n Z = clock pulse (low to high) ZZ = clock pulse (high to low) www.onsemi.com 2