3.3 V/5 VECL Quad 2-Input Differential AND/NAND MC10EP105, MC100EP105 Description The MC10/100EP105 is a quad 2input differential AND/NAND www.onsemi.com gate. Each gate is functionally equivalent to the EP05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP105 is ideal for applications requiring the fastest AC performance available. The 100 Series contains temperature compensation. Features LQFP32 275 ps Typical Propagation Delay FA SUFFIX Maximum Frequency > 3 GHz Typical CASE 561AB PECL Mode Operating Range: V = 3.0 V to 5.5 V CC with V = 0 V EE MARKING DIAGRAMS* NECL Mode Operating Range: V = 0 V CC with V = 3.0 V to 5.5 V EE Open Input Default State MCxxx EP105 Safety Clamp on Inputs AWLYYWWG These Devices are Pb-Free, Halogen Free and are RoHS Compliant xxx = 10 or 100 A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = PbFree Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Device Package Shipping LQFP32 MC10EP105FAG 250 Units / Tray (PbFree) MC100EP105FAG LQFP32 250 Units / Tray (PbFree) For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2006 1 Publication Order Number: April, 2021 Rev. 12 MC10EP105/DMC10EP105, MC100EP105 D0b D1a D1a D1b D1b D2a D2a D2b 24 23 22 21 20 19 18 17 25 16 D0b D2b 26 15 D0a D3a 27 14 D0a D3a MC10EP105 28 13 V V EE CC MC100EP105 29 12 Q0 D3b 30 11 Q0 D3b 31 10 V V CC EE 32 9 V NC CC 123456 78 V Q1 Q1 Q2 Q2 Q3 Q3 V CC CC Warning: All V and V pins must be externally connected CC EE to Power Supply to guarantee proper operation. Figure 1. 32 Lead LQFP Pinout (Top View) D0a Table 1. PIN DESCRIPTION Q0 D0a PIN FUNCTION D0b Dna*, Dnb*, Dna*, Dnb* ECL Data Inputs Q0 D0b Qn, Qn ECL Data Outputs V Positive Supply CC D1a Q1 V Negative Supply EE D1a D1b NC No Connect Q1 D1b * Pins will default LOW when left open. D2a Q2 D2a Table 2. TRUTH TABLE D2b Q2 Dna Dnb Dna Dnb Qn Qn D2b LL H H L H D3a Q3 L HHL L H D3a H LLH LH D3b HH L L H L Q3 D3b V EE Figure 2. Logic Diagram www.onsemi.com 2