MC100LVE222 3.3 V/5.0 VECL 1:15 Differential 1/2 Clock Driver The MC100LVE222 is a low skew 1:15 differential 1/2 ECL fanout buffer designed with clock distribution in mind. The LVECL/LVPECL input signal pairs can be differential or used single-ended (with V output reference bypassed and connected to the BB MC100LVE222 Table 1. PIN DESCRIPTION PIN FUNCTION CLK0, CLK0 ECL Differential Input Clock 39 38 37 36 35 34 33 32 31 30 29 28 27 40 26 CLK1, CLK1 ECL Differential Input Clock VCCO Qd0 CLK Sel ECL Clock Select 41 25 Qb2 Qd0 MR ECL Master Reset 42 24 Qb2 Qd1 Qa0:1, Qa0:1 ECL Differential Outputs 43 23 Qb0:2, Qb0:2 ECL Differential Outputs Qb1 Qd1 Qc0:3, Qc0:3 ECL Differential Outputs 44 22 Qb1 Qd2 Qd0:5, Qd0:5 ECL Differential Outputs 45 21 Qb0 Qd2 fseln ECL 1 or 2 Select MC100LVE222 46 20 V Reference Voltage Output Qb0 Qd3 BB V /V Positive Supply (V = V ) CC CCO CC CCO 47 19 VCCO Qd3 V Negative Supply EE 48 18 Qa1 Qd4 No Connect NC 49 17 Qa1 Qd4 Note: All V /V , and V pins must be CC CCO EE 50 16 externally connected to Power Supply to Qa0 Qd5 guarantee proper operation. All V /V pins CC CCO 51 15 Qa0 Qd5 are internally interconnected. 52 14 VCCO VCCO 12 34 56 78 9 10 11 12 13 Table 2. FUNCTION TABLE Function Input LH MR Active Reset CLK Sel CLK0 CLK1 Figure 1. Pinout Assignment (Top View) fseln 1 2 MR CLK0 CLK0 1 2 Qa0:1 CLK1 Qa0:1 2 CLK1 CLK Sel V BB fsela 3 Qb0:2 Qb0:2 fselb 4 Qc0:3 Qc0:3 fselc Qd0:5 6 Qd0:5 fseld Figure 2. Logic Diagram