MC74AC161, MC74ACT161, MC74AC163, MC74ACT163 Synchronous Presettable Binary Counter The MC74AC161/74ACT161 and MC74AC163/74ACT163 are high speed synchronous modulo 16 binary counters. They are MC74AC161, MC74ACT161, MC74AC163, MC74ACT163 operation, as shown in the Mode Select Table. A LOW signal on MR overrides all other inputs and asynchronously PE P P P P 0 1 2 3 forces all outputs LOW. A LOW signal on SR overrides CEP counting and parallel loading and allows all outputs to go CET TC CP LOW on the next rising edge of CP. A LOW signal on PE *R Q Q Q Q 0 1 2 3 overrides counting and allows information on the Parallel Data (P ) inputs to be loaded into the flipflops on the next n rising edge of CP. With PE and MR (161) or SR ( 163) *MR for 161 HIGH, CEP and CET permit counting when both are HIGH. *SR for 163 Conversely, a LOW signal on either CEP or CET inhibits counting. Figure 2. Logic Symbol The MC74AC161/ACT161 and MC74AC163/ACT163 use D type edgetriggered flipflops and changing the SR, PE, FUNCTIONAL DESCRIPTION CEP and CET inputs when the CP is in either state does not The MC74AC161/ACT161 and MC74AC163/ACT163 cause errors, provided that the recommended setup and hold count modulo16 binary sequence. From state 15 (HHHH) times, with respect to the rising edge of CP, are observed. they increment to state 0 (LLLL). The clock inputs of all The Terminal Count (TC) output is HIGH when CET is flipflops are driven in parallel through a clock buffer. Thus HIGH and counter is in state 15. To implement synchronous all changes of the Q outputs (except due to Master Reset of multistage counters, the TC outputs can be used with the the 161) occur as a result of, and synchronous with, the CEP and CET inputs in two different ways. Please refer to LOWtoHIGH transition of the CP input signal. The the MC74AC568 data sheet. The TC output is subject to circuits have four fundamental modes of operation, in order decoding spikes due to internal race conditions and is of precedence: asynchronous reset (161), synchronous reset therefore not recommended for use as a clock or ( 163), parallel load, countup and hold. Five control inputs asynchronous reset for flip flops, counters or registers. Master Reset (MR, 161), Synchronous Reset (SR, 163), Logic Equations: Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable = CEPCETPE Count Enable Trickle (CET) determine the mode of TC = Q Q Q Q CET 0 1 2 3 0 1 2 3 4 MODE SELECT TABLE Action on the Rising 15 5 PE *SR CET CEP Clock Edge ( ) L X X X Reset (Clear) 14 6 H L X X Load (P Q ) n n H H H H Count (Increment) 13 7 H H L X No Change (Hold) H H X L No Change (Hold) 12 11 10 9 8 *For 163 only H = HIGH Voltage Level Figure 3. State Diagram L = LOW Voltage Level X = Immaterial