MC74AC257, MC74ACT257 Quad 2-Input Multiplexer with 3-State Outputs The MC74AC257/74ACT257 is a quad 2input multiplexer with 3state outputs. Four bits of data from two sources can be selected using a Common Data Select input. The four outputs present the www.onsemi.com selected data in true (noninverted) form. The outputs may be switched to a high impedance state by placing a logic HIGH on the common MARKING Output Enable (OE) input, allowing the outputs to interface directly DIAGRAMS with busoriented systems. 16 Multiplexer Expansion by Tying Outputs Together SOIC16 xxx257G Noninverting 3State Outputs D SUFFIX 16 AWLYWW CASE 751B Outputs Source/Sink 24 mA 1 1 ACT257 Has TTL Compatible Inputs 16 These are PbFree Devices xxx TSSOP16 257 16 V OE I I Z I I Z CC 0c 1c c 0d 1d d DT SUFFIX ALYW 16 15 14 13 12 11 10 9 CASE 948F 1 1 xxx = AC or ACT A = Assembly Location WL or L = Wafer Lot Y = Year WW or W = Work Week 1 2 345 67 8 G or = PbFree Package SI I Z I I Z GND 0a 1a a 0b 1b b (Note: Microdot may be in either location) Figure 1. Pinout: 16Lead Packages Conductors (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: March, 2015 Rev. 8 MC74AC257/DMC74AC257, MC74ACT257 FUNCTIONAL DESCRIPTION PIN NAME The MC74AC257/74ACT257 is a quad 2input PIN FUNCTION multiplexer with 3state outputs. It selects four bits of data S Common Data Select Input from two sources under control of a Common Data Select OE 3State Output Enable Input input. When the Select input is LOW, the I inputs are 0x I I Data Inputs from Source 0 0a 0d selected and when Select is HIGH, the I inputs are 1x selected. The data on the selected inputs appears at the I I Data Inputs from Source 1 1a 1d outputs in true (noninverted) form. The device is the logic Z Z 3State Multiplexer Outputs a d implementation of a 4pole, 2position switch where the position of the switch is determined by the logic levels TRUTH TABLE supplied to the Select input. The logic equations for the Output Select Data outputs are shown below: Outputs Enable Input Inputs Z = OE(I S+I S) a 1a 0a OE S I I Z 0 1 Z = OE(I S+I S) b 1b 0b H X X X Z Z = OE(I S+I S) c 1c 0c L H X LL Z = OE(I S+I S) L H X HH d 1d 0d L L L XL When the Output Enable input (OE) is HIGH, the outputs L L H X H are forced to a high impedance state. If the outputs are tied H = HIGH Voltage Level together, all but one device must be in the high impedance L = LOW Voltage Level state to avoid high currents that would exceed the maximum X = Immaterial Z = High Impedance ratings. Designers should ensure the Output Enable signals to 3state devices whose outputs are tied together are designed so there is no overlap. OE I I I I I I I I 0a 1a 0b 1b 0c 1c 0d 1d S Z Z Z Z a b c d Figure 2. Logic Symbol OE I I I I I I I I S 0a 1a 0b 1b 0c 1c 0d 1d Z Z Z Z a b c d NOTE: This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Figure 3. Logic Diagram www.onsemi.com 2