Product Information

MC74HC73ADTR2G

MC74HC73ADTR2G electronic component of ON Semiconductor

Datasheet
ON Semiconductor Flip Flops DUAL J-K FLIPFLOP W RESET

Manufacturer: ON Semiconductor
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Price (USD)

1: USD 0.5177 ea
Line Total: USD 0.52

223 - Global Stock
Ships to you between
Fri. 24 May to Wed. 29 May
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
223 - WHS 1


Ships to you between
Fri. 24 May to Wed. 29 May

MOQ : 1
Multiples : 1

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MC74HC73ADTR2G
ON Semiconductor

1 : USD 0.5177
10 : USD 0.4009
30 : USD 0.3425
100 : USD 0.2861
500 : USD 0.2499
1000 : USD 0.2317

     
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MC74HC73A Dual J-K Flip-Flop with Reset HighPerformance SiliconGate CMOS The MC74HC73A is identical in pinout to the LS73. The device inputs are compatible with standard CMOS outputs with pullup www.onsemi.com resistors, they are compatible with LSTTL outputs. Each flipflop is negativeedge clocked and has an activelow MARKING asynchronous reset. DIAGRAMS The MC74HC73A is identical in function to the HC107, but has a different pinout. 14 Features SOIC14 HC73AG 14 D SUFFIX Output Drive Capability: 10 LSTTL Loads AWLYWW CASE 751A 1 Outputs Directly Interface to CMOS, NMOS, and TTL 1 Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 A 14 High Noise Immunity Characteristic of CMOS Devices TSSOP14 HC 14 73A DT SUFFIX In Compliance with the JEDEC Standard No. 7.0 A Requirements ALYW CASE 948G 1 Chip Complexity: 92 FETs or 23 Equivalent Gates 1 NLV Prefix for Automotive and Other Applications Requiring A = Assembly Location Unique Site and Control Change Requirements AECQ100 WL, L = Wafer Lot Qualified and PPAP Capable YY, Y = Year These are PbFree Devices WW, W = Work Week G or = PbFree Package LOGIC DIAGRAM PIN ASSIGNMENT (Note: Microdot may be in either location) 14 J1 12 CLOCK 1 1 14 J1 Q1 1 RESET 1 2 13 Q1 CLOCK 1 ORDERING INFORMATION 13 Q1 3 K1 3 12 Q1 See detailed ordering and shipping information in the package K1 dimensions section on page 5 of this data sheet. V 4 11 GND CC 2 RESET 1 CLOCK 2 5 10 K2 7 RESET 2 6 9 Q2 J2 9 Q2 J2 7 8 Q2 5 CLOCK 2 8 Q2 10 K2 6 RESET 2 PIN 4 = V CC PIN 11 = GND FUNCTION TABLE Inputs Outputs Reset Clock J K Q Q LX X X L H H L L No Change HLHLH HHLHL H H H Toggle H L X X No Change H H X X No Change H X X No Change Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: January, 2016 Rev. 10 MC74HC73/DMC74HC73A MAXIMUM RATINGS Symbol Parameter Value Unit This device contains protection circuitry to guard against damage V DC Supply Voltage (Referenced to GND) 0.5 to + 7.0 V CC due to high static voltages or electric V DC Input Voltage (Referenced to GND) 1.5 to V + 1.5 V in CC fields. However, precautions must be taken to avoid applications of any V DC Output Voltage (Referenced to GND) 0.5 to V + 0.5 V out CC voltage higher than maximum rated I DC Input Current, per Pin 20 mA voltages to this highimpedance cir- in cuit. For proper operation, V and in I DC Output Current, per Pin 25 mA out V should be constrained to the out I DC Supply Current, V and GND Pins 50 mA range GND (V or V ) V . CC CC in out CC Unused inputs must always be P Power Dissipation in Still Air SOIC Package 500 mW D tied to an appropriate logic voltage level (e.g., either GND or V ). T Storage Temperature 65 to + 150 C CC stg Unused outputs must be left open. T C Lead Temperature, 1 mm from Case for 10 Seconds L (PSOIC Package) 260 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Derating SOIC Package: 7 mW/ C from 65 to 125 C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit V DC Supply Voltage (Referenced to GND) 2.0 6.0 V CC V , V DC Input Voltage, Output Voltage (Referenced to GND) 0 V V in out CC T Operating Temperature, All Package Types 55 + 125 C A t , t ns Input Rise and Fall Time V = 2.0 V 0 1000 r f CC (Figure 1) V = 4.5 V 0 500 CC V = 6.0 V 0 400 CC Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit V 55 to CC V 25 C 85 C 125 C Symbol Parameter Test Conditions Unit V Minimum HighLevel Input V = 0.1 V or V 0.1 V 2.0 1.5 1.5 1.5 V IH out CC Voltage I 20 A 4.5 3.15 3.15 3.15 out 6.0 4.2 4.2 4.2 V V Maximum LowLevel Input V = 0.1 V or V 0.1 V 2.0 0.3 0.3 0.3 IL out CC Voltage I 20 A 4.5 0.9 0.9 0.9 out 6.0 1.2 1.2 1.2 V Minimum HighLevel Output V OH V = V or V 2.0 1.9 1.9 1.9 in IH IL Voltage I 20 A 4.5 4.4 4.4 4.4 out 6.0 5.9 5.9 5.9 V = V or V I 4.0 mA 4.5 3.98 3.84 3.70 in IH IL out I 5.2 mA 6.0 5.48 5.34 5.20 out V V Maximum LowLevel Output V = V or V 2.0 0.1 0.1 0.1 OL in IH IL Voltage I 20 A 4.5 0.1 0.1 0.1 out 6.0 0.1 0.1 0.1 V = V or V I 4.0 mA 4.5 0.26 0.33 0.40 in IH IL out I 5.2 mA 6.0 0.26 0.33 0.40 out I Maximum Input Leakage Current V = V or GND 6.0 0.1 1.0 1.0 A in in CC I Maximum Quiescent Supply 6.0 4 40 80 A V = V or GND CC in CC Current (per Package) I = 0 A out Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 2

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
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