Product Information

MC74LCX373DWR2G

MC74LCX373DWR2G electronic component of ON Semiconductor

Datasheet
Latch Transparent 3-ST 8-CH D-Type 20-Pin SOIC W T/R

Manufacturer: ON Semiconductor
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1000: USD 0.2865 ea
Line Total: USD 286.5

0 - Global Stock
MOQ: 1000  Multiples: 1000
Pack Size: 1000
Availability Price Quantity
0 - Global Stock


Ships to you between Fri. 03 May to Thu. 09 May

MOQ : 1000
Multiples : 1000

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MC74LCX373DWR2G
ON Semiconductor

1000 : USD 0.4834

0 - Global Stock


Ships to you between Fri. 03 May to Thu. 09 May

MOQ : 859
Multiples : 859

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MC74LCX373DWR2G
ON Semiconductor

859 : USD 0.49

0 - Global Stock


Ships to you between Thu. 09 May to Mon. 13 May

MOQ : 1
Multiples : 1

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MC74LCX373DWR2G
ON Semiconductor

1 : USD 2.9515
10 : USD 1.1111
25 : USD 1.0118
100 : USD 0.8316
250 : USD 0.7767
500 : USD 0.6866
1000 : USD 0.5427

0 - Global Stock


Ships to you between Fri. 03 May to Thu. 09 May

MOQ : 1000
Multiples : 1000

Stock Image

MC74LCX373DWR2G
ON Semiconductor

1000 : USD 0.2865
1100 : USD 0.2647
2200 : USD 0.2586
5500 : USD 0.2523
11000 : USD 0.2472

     
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RoHS - XON
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MC74LCX373 Low-Voltage CMOS Octal Transparent Latch With 5 VTolerant Inputs and Outputs (3State, NonInverting) www.onsemi.com The MC74LCX373 is a high performance, noninverting octal transparent latch operating from a 2.3 to 3.6 V supply. High MARKING impedance TTL compatible inputs significantly reduce current DIAGRAMS loading to input drivers while TTL compatible outputs offer improved switching noise performance. A V specification of 5.5 V allows I 20 MC74LCX373 inputs to be safely driven from 5 V devices. SOIC20 WB 20 LCX373 The MC74LCX373 contains 8 Dtype latches with 3state outputs. DW SUFFIX AWLYYWWG When the Latch Enable (LE) input is HIGH, data on the Dn inputs CASE 751D 1 enters the latches. In this condition, the latches are transparent, i.e., 1 a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D 20 inputs a setup time preceding the HIGHtoLOW transition of LE. The 3state standard outputs are controlled by the Output Enable (OE) LCX TSSOP20 373 input. When OE is LOW, the standard outputs are enabled. When OE 20 DT SUFFIX ALYW is HIGH, the standard outputs are in the high impedance state, but this CASE 948E 1 does not interfere with new data entering into the latches. 1 Features LCX373 = Specific Device Code Designed for 2.3 to 3.6 V V Operation CC A = Assembly Location 5 V Tolerant Interface Capability With 5 V TTL Logic L, WL = Wafer Lot Y, YY = Year Supports Live Insertion and Withdrawal W, WW = Work Week G or = PbFree Package I Specification Guarantees High Impedance When V = 0 V OFF CC (Note: Microdot may be in either location) LVTTL Compatible LVCMOS Compatible 24 mA Balanced Output Sink and Source Capability ORDERING INFORMATION See detailed ordering and shipping information in the package Near Zero Static Supply Current in all Three Logic States (10 A) dimensions section on page 6 of this data sheet. Substantially Reduces System Power Requirements Latchup Performance Exceeds 500 mA ESD Performance: Human Body Model >2000 V Machine Model >200 V NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements AECQ100 Qualified and PPAP Capable These Devices are PbFree, Halogen Free/BFR Free and are RoHS Compliant Semiconductor Components Industries, LLC, 2013 1 Publication Order Number: June, 2017 Rev. 14 MC74LCX373/DMC74LCX373 1 OE 11 LE V O7 D7 D6 O6 O5 D5 D4 O4 LE 2 CC LE 3 O0 Q 20 19 18 17 16 15 14 13 12 11 D0 D 5 LE 4 O1 Q D1 D 6 1 2 3 4 567 9 LE 8 10 7 O2 Q D2 D OE O0 D0 D1 O1 O2 D2 D3 O3 GND Figure 1. Pinout (Top View) 9 LE 8 O3 Q D3 D 12 LE 13 O4 Q D4 D PIN NAMES PINS FUNCTION 15 LE OE Output Enable Input 14 O5 Q D5 D LE Latch Enable Input D0D7 Data Inputs 16 LE O0O7 3State Latch Outputs 17 O6 Q D6 D 19 LE O7 18 Q D7 D Figure 2. Logic Diagram TRUTH TABLE INPUTS OUTPUTS OE LE Dn On OPERATING MODE L H H H Transparent (Latch Disabled) Read Latch L H L L L L h H Latched (Latch Enabled) Read Latch L L l L L L X NC Hold Read Latch H L X Z Hold Disabled Outputs H H H Z Transparent (Latch Disabled) Disabled Outputs H H L Z H L h Z Latched (Latch Enabled) Disabled Outputs H L l Z H = High Voltage Level h = High Voltage Level One Setup Time Prior to the Latch Enable HightoLow Transition L = Low Voltage Level l = Low Voltage Level One Setup Time Prior to the Latch Enable HightoLow Transition NC = No Change, State Prior to the Latch Enable HightoLow Transition X = High or Low Voltage Level or Transitions are Acceptable Z = High Impedance State For I Reasons DO NOT FLOAT Inputs CC www.onsemi.com 2

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Aptina / ON Semiconductor
FAIRCHILD
FAIRCHILD (ON SEMICONDUCTOR)
Fairchild Semiconductor
FS8
FSC
ON
ON SEMI
ON Semicon
ON SEMICONDUCTOR
ON SEMICONDUCTOR (FAIRCHILD)
ON Semiconductor / Fairchild
ON4
ON5
onsemi
ON-SEMI
onsemi / Fairchild
OOF
Xsens / Fairchild

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