www.fairchildsemi.com ML4824 Power Factor Correction and PWM Controller Combo Features General Description Internally synchronized PFC and PWM in one IC The ML4824 is a controller for power factor corrected, Low total harmonic distortion switched mode power supplies. Power Factor Correction (PFC) allows the use of smaller, lower cost bulk capacitors, Reduces ripple current in the storage capacitor between reduces power line loading and stress on the switching FETs, the PFC and PWM sections and results in a power supply that fully complies with Average current, continuous boost leading edge PFC IEC1000-2-3 specication. The ML4824 includes circuits Fast transconductance error amp for voltage loop for the implementation of a leading edge, average current, High efciency trailing edge PWM can be congured for boost type power factor correction and a trailing edge, current mode or voltage mode operation pulse width modulator (PWM). Average line voltage compensation with brownout control The device is available in two versions the ML4824-1 (fPWM PFC overvoltage comparator eliminates output = fPFC) and the ML4824-2 (fPWM = 2 x fPFC). Doubling the runaway due to load removal switching frequency of the PWM allows the user to design Current fed gain modulator for improved noise immunity with smaller output components while maintaining the best Overvoltage protection, UVLO, and soft start operating frequency for the PFC. An over-voltage compara- tor shuts down the PFC section in the event of a sudden decrease in load. The PFC section also includes peak current limiting and input voltage brown-out protection. The PWM section can be operated in current or voltage mode at up to 250kHz and includes a duty cycle limit to prevent trans- former saturation. Block Diagram 16 1 13 IEAO POWER FACTOR CORRECTOR V VEAO CC V CCZ OVP V V REF VEA FB 13.5V 7.5V + IEA 14 3.5k 15 REFERENCE + 2.7V 2.5V + + S Q I AC 2 1V + GAIN V R Q RMS MODULATOR 4 PFC OUT 3.5k PFC I I LIMIT S Q SENSE 12 3 R Q RAMP 1 7 OSCILLATOR x 2 RAMP 2 (-2 VERSION ONLY) DUTY CYCLE 8 LIMIT 8V V 1.25V DC 6 + PWM OUT V S Q CC 11 V OK IN V 50 A FB SS + 1V R Q 5 2.5V + + DC I LIMIT 8V DC I LIMIT 9 V UVLO CCZ PULSE WIDTH MODULATOR REV. 1.0.6 11/7/03 ML4824 PRODUCT SPECIFICATION Pin Conguration ML4824 16-Pin PDIP (P16) 16-Pin Wide SOIC (S16W) IEAO 1 16 VEAO I 2 15 V AC FB I 3 14 V SENSE REF V 4 13 V RMS CC SS 5 12 PFC OUT V 6 11 PWM OUT DC RAMP 1 7 10 GND RAMP 2 8 9 DC I LIMIT TOP VIEW Pin Description PIN NAME FUNCTION 1 IEAO PFC transconductance current error amplifier output 2I PFC gain control reference input AC 3I Current sense input to the PFC current limit comparator SENSE 4V Input for PFC RMS line voltage compensation RMS 5 SS Connection point for the PWM soft start capacitor 6V PWM voltage feedback input DC 7 RAMP 1 Oscillator timing node timing set by R C T T 8 RAMP 2 When in current mode, this pin functions as as the current sense input when in voltage mode, it is the PWM input from PFC output (feed forward ramp). 9 DC I PWM current limit comparator input LIMIT 10 GND Ground 11 PWM OUT PWM driver output 12 PFC OUT PFC driver output 13 V Positive supply (connected to an internal shunt regulator) CC 14 V Buffered output for the internal 7.5V reference REF 15 V PFC transconductance voltage error amplifier input FB 16 VEAO PFC transconductance voltage error amplifier output 2 REV. 1.0.6 11/7/03