Product Information


Product Image X-ON

Clock Divider 15-OUT 52-Pin QFN EP Tray

Manufacturer: ON Semiconductor
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges

Price (USD)

260: USD 15.4846 ea
Line Total: USD 4025.996

0 - Global Stock
MOQ: 260  Multiples: 260
Pack Size: 260
Availability Price Quantity
0 - Global Stock

Ships to you between Fri. 16 Jun to Thu. 22 Jun

MOQ : 260
Multiples : 260

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ON Semiconductor

260 : USD 15.4846

ON Semiconductor
Product Category
Clock Drivers & Distribution
Multiply/Divide Factor
Output Type
Lvecl, Lvpecl
Max Output Freq
1 Ghz
Supply Voltage - Max
+/- 3.8 V
Supply Voltage - Min
+/- 2.375 V
Package / Case
QFN - 52
Minimum Operating Temperature
- 40 C
Maximum Operating Temperature
+ 85 C
Mounting Style
Input Type
Lvecl, Lvpecl
Differential Divider Multiplexer
On Semiconductor
Operating Supply Current
130 mA
Factory Pack Quantity :
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NB100LVEP222 2.5 V/3.3 V 2:1:15 Differential ECL/PECL 1/2 Clock Driver The NB100LVEP222 is a low skew 2:1:15 differential 1/2 ECL fanout buffer designed with clock distribution in mind. The LVECL/LVPECL input signal pairs can be used in a differential configuration or singleended (with V output reference bypassed BB MARKING and connected to the unused input of a pair). Either of two fully DIAGRAMS* differential clock inputs may be selected. Each of the four output 52 banks of 2, 3, 4, and 6 differential pairs may be independently 1 configured to fanout 1X or 1/2X of the input frequency. When the NB100 output banks are configured with the 1 mode, data can also be LVEP222 distributed. The LVEP222 specifically guarantees low output to output LQFP52 AWLYYWWG skew. Optimal design, layout, and processing minimize skew within a FA SUFFIX device and from lot to lot. This device is an improved version of the CASE 848H MC100LVE222 with higher speed capability and reduced skew. The fsel pins and CLK_Sel pin are asynchronous control inputs. 52 Any changes may cause indeterminate output states requiring an MR 1 pulse to resynchronize any 1/2X outputs (See Figure 4). Unused output pairs should be left unterminated (open) to reduce power and NB100 switching noise. LVEP222 The NB100LVEP222, as with most ECL devices, can be operated 152 AWLYYWWG from a positive V /V supply in LVPECL mode. This allows the CC CC0 QFN52 LVEP222 to be used for high performance clock distribution in MN SUFFIX CASE 485M +2.5/3.3 V systems. In a PECL environment series or Thevenin line, terminations are typically used as they require no additional power supplies. For more information on using PECL, designers should refer A = Assembly Location to Application Note AN1406/D. For a SPICE model, refer to WL = Wafer Lot Application Note AN1560/D. YY = Year The V pin, an internally generated voltage supply, is available to BB WW = Work Week this device only. For singleended LVPECL input conditions, the G = PbFree Package unused differential input is connected to V as a switching reference BB *For additional marking information, refer to voltage. V may also rebias AC coupled inputs. When used, decouple BB Application Note AND8002/D. V and V /V via a 0.01 F capacitor and limit current sourcing BB CC CC0 or sinking to 0.5mA. When not used, V should be left open. BB Singleended CLK input operation is limited to a V /V 3.0 V in CC CC0 ORDERING INFORMATION LVPECL mode, or V  3.0 V in NECL mode. EE See detailed ordering and shipping information in the package Features dimensions section on page 11 of this data sheet. 20 ps OutputtoOutput Skew 85 ps ParttoPart Skew Selectable 1x or 1/2x Frequency Outputs LVPECL Mode Operating Range: V /V = 2.375 V to 3.8 V with V = 0 V CC CC0 EE NECL Mode Operating Range: V /V = 0 V with V = 2.375 V to 3.8 V CC CC0 EE Internal Input Pulldown Resistors Performance Upgrade to ON Semiconductors MC100LVE222 V Output BB These Devices are PbFree and are RoHS Compliant Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: April, 2015 Rev. 13 NB100LVEP222/DNB100LVEP222 39 38 37 36 35 34 33 32 31 30 29 28 27 40 26 V Qd0 CC0 41 25 Qb2 Qd0 42 24 Qb2 Qd1 43 23 Qb1 Qd1 44 22 Qb1 Qd2 45 21 Qb0 Qd2 46 20 Qb0 NB100LVEP222 Qd3 47 19 V Qd3 CC0 Qd4 Qa1 48 18 Qa1 Qd4 49 17 Qd5 Qa0 50 16 Qd5 Qa0 51 15 V V 52 14 CC0 CC0 1 2345678 910 11 12 13 All V , V , and V pins must be externally connected to appropriate Power Supply to guarantee proper operation.V pin internally CC CC0 EE CC connected to V pins. The thermally conductive exposed pad on package bottom (see package case drawing) must be attached to a CC0 heatsinking conduit. This exposed pad is electrically connected to V internally. EE Figure 1. 52Lead LQFP Pinout (Top View) 2 V V CC CC0 MR Qc0 Qc0 fsela Qc1 fselb CLK0 Qc1 Qc2 CLK0 Qc2 CLK_Sel Qc3 CLK1 Qc3 CLK1 V V CC0 BB NC fselc NC fseld V V CC0 EE

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
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