NB3N3002 3.3V, Crystal to 25MHz, 100MHz, 125MHz and 200MHz HCSL Clock Generator www.onsemi.com Description The NB3N3002 is a precision, low phase noise clock generator that MARKING supports PCIExpress and Ethernet requirements. The device accepts DIAGRAM a 25 MHz fundamental mode parallel resonant crystal and generates a 16 differential HCSL output at 25 MHz, 100 MHz, 125 MHz or 200 MHz 16 NB3N clock frequencies. Outputs can interface with LVDS with proper 3002 termination (See Figure 5). 1 ALYW This device is housed in 5.0 mm x 4.4 mm narrow body TSSOP 16 TSSOP16 1 DT SUFFIX pin package. CASE 948F Features A = Assembly Location Uses 25 MHz Fundamental Mode Parallel Resonant Crystal L = Wafer Lot Y = Year External Loop Filter is Not Required W = Work Week HCSL Differential Output or LVDS with Proper Termination = PbFree Package For Selectable Multipliers of the Input Frequency (Note: Microdot may be in either location) Output Enable with TriState Outputs PCIe Gen1, Gen2, Gen3, Gen4, QPI, UPI Jitter Compliant ORDERING INFORMATION Typical TIE RMS jitter of 2.5 ps See detailed ordering and shipping information in the package Phase Noise: 100 MHz dimensions section on page 6 of this data sheet. Offset Noise Power 100 Hz 109.4 dBc 1 kHz 127.8 dBc 10 kHz 136.2 dBc 100 kHz 138.8 dBc 1 MHz 138.2 dBc 10 MHz 161.4 dBc 20 MHz 163.00 dBc Operating Range 3.3 V 5% Industrial Temperature Range 40C to +85C These are PbFree Devices VDD X1/CLK CLK Clock Buffer Phase Charge HSCL VCO 25 MHz Clock or Crystal Oscillator Detector Pump Output Crystal X2 CLK M GND SEL0 SEL1 OE IREF Figure 1. NB3N3002 Simplified Logic Diagram Semiconductor Components Industries, LLC, 2013 1 Publication Order Number: May, 2017 Rev. 7 NB3N3002/DNB3N3002 SEL0 1 16 VDD SEL1 2 15 CLK GND 3 14 CLK X1/CLK 4 13 GND X2 5 12 VDD OE 6 11 NC GND 7 10 NC GND 8 9 IREF Figure 2. Pin Configuration (Top View) Table 1. PIN DESCRIPTION Pin Symbol I/O Description 1 Sel0 Input LVTTL/LVCMOS frequency select input 0. Internal pullup resistor to V . See output DD select table 2 for details. 2 Sel1 Input LVTTL/LVCMOS frequency select input 1. Internal pullup resistor to V . See output DD select Table 2 for details. 12, 16 V Power Supply Positive supply voltage pins are connected to +3.3 V supply voltage. DD 4 X1/CLK Input Crystal or Clock input. Connect to 25 MHz crystal source or singleended clock. 5 X2 Input Crystal input. Connect to a 25 MHz crystal or leave unconnected for clock input. 6 OE Input Output enable tristates output when connected to GND. Internal pullup resistor to V . DD 3, 7, 8, 13 GND Power Supply Ground 0 V. These pins provide GND return path for the devices. 9 I Output Output current reference pin. Precision resistor (typ. 475 ) is connected from pin 9 to REF GND to set the output current. 15 CLK HCSL or Noninverted clock output. (For LVDS levels see Figure 5) LVDS Output 14 CLK HCSL or Inverted clock output. (For LVDS levels see Figure 5) LVDS Output 10,11 NC Do not connect Recommended Crystal Parameters Table 2. OUTPUT FREQUENCY SELECT TABLE WITH 25MHz CRYSTALS Crystal Fundamental ATCut Frequency 25 MHz SEL1* SEL0* CLK Multiplier f (MHz) CLK Load Capacitance 1620 pF L L 1x 25 Shunt Capacitance, C0 7 pF Max L H 4x 100 Equivalent Series Resistance 50 Max Initial Accuracy at 25 C 20 ppm H L 5x 125 Temperature Stability 30 ppm H H 8x 200 Aging 20 ppm *Pins SEL1 and SEL0 default high when left open. www.onsemi.com 2