NB4L52 2.5 V/3.3 V/5.0 V Differential Data/Clock D Flip-Flop with Reset MultiLevel Inputs to LVPECL Translator NB4L52 V R R V TR TR 16 15 14 13 1 12 V V TD CC 11 D 2 Q NB4L52 D 3 10 Q V 4 9 V TD EE 5 678 V CLK CLK V TCLK TCLK Exposed Pad (EP) Figure 2. Pinout (Top View) Table 2. PIN DESCRIPTION Pin Name I/O Description 1 V Internal 50 Termination Pin. (See Table 4) TD 2 D ECL, CML, LVCMOS, Noninverted Differential Input. (Note 1) LVDS, LVTTL Input 3 D ECL, CML, LVCMOS, Inverted Differential Input. (Note 1) LVDS, LVTTL Input 4 V Internal 50 Termination Pin. (See Table 4) TD 5 V Internal 50 Termination Pin. (See Table 4) TCLK 6 CLK ECL, CML, LVCMOS, Noninverted Differential Input. (Note 1) LVDS, LVTTL Input 7 CLK ECL, CML, LVCMOS, Inverted Differential Input. (Note 1) LVDS, LVTTL Input 8 V Internal 50 Termination Pin. (See Table 4) TCLK 9 V Negative Supply Voltage EE 10 Q ECL Output Inverted Differential Output. Typically terminated with 50 resistor to V 2.0 V. CC 11 Q ECL Output Noninverted Differential Output. Typically terminated with 50 resistor to V 2.0 V. CC 12 V Positive Supply Voltage CC 13 V Internal 50 Termination Pin. (See Table 4) TR 14 R LVECL, LVCMOS, Noninverted Differential Reset Input. (Note 1) LVTTL Input 15 R LVECL, LVCMOS, Inverted Differential Reset Input. (Note 1) LVTTL Input 16 V Internal 50 Termination Pin. (See Table 4) TR EP The Exposed Pad (EP) on the QFN16 package bottom is thermally connected to the die for improved heat transfer out of package. The pad is not electrically connected to the die, but is recommended to be electrically and thermally connected to V on the PC board. EE 1. In the differential configuration when the input termination pin (VTD, VTD, VTR, VTR, VTCLK, VTCLK) are connected to a common termination voltage or left open, and if no signal is applied on D/D,CLK/CLK,R/R input then the device will be susceptible to selfoscillation.