NB6N14SMNG

NB6N14S 3.3 V 1:4 AnyLevel Differential Input to LVDS Fanout Buffer/Translator The NB6N14S is a differential 1:4 Clock or Data Receiver and will accept AnyLevel differential input signals: LVPECL, CML or NB6N14S Q0 Q0 V GND Exposed Pad (EP) CC 16 15 14 13 Table 1. TRUTH TABLE Q1 1 12 IN IN IN EN Q Q Q1 2 11 V T 01 1 0 1 NB6N14S Q2 3 10 V 10 1 1 0 REF AC x x 0 0 (Note 1) 1 (Note 1) Q2 4 9 IN 1. On next transition of the input signal (IN). 56 7 8 Q3 Q3 V EN CC Figure 3. NB6N14S Pinout, 16pin QFN (Top View) Table 2. PIN DESCRIPTION Pin Name I/O Description 1 Q1 LVDS Output Noninverted IN output. Typically loaded with 100 receiver termination resistor across differential pair. 2 Q1 LVDS Output Inverted IN output. Typically loaded with 100 receiver termination resistor across differential pair. 3 Q2 LVDS Output Noninverted IN output. Typically loaded with 100 receiver termination resistor across differential pair. 4 Q2 LVDS Output Inverted IN output. Typically loaded with 100 receiver termination resistor across differential pair. 5 Q3 LVDS Output Noninverted IN output. Typically loaded with 100 receiver termination resistor across differential pair. 6 Q3 LVDS Output Inverted IN output. Typically loaded with 100 receiver termination resistor across differential pair. 7 V Positive Supply Voltage. CC 8 EN LVTTL / LVCMOS Input Synchronous Output Enable. When LOW, Q outputs will go LOW and Qb outputs will go HIGH on the next negative transition of IN input. The internal DFF register is clocked on the falling edge of IN input see Figure 23. The EN pin has an internal pullup resistor and defaults HIGH when left open. 9 IN LVPECL, CML, LVDS Inverted Differential Input 10 V LVPECL Output The V reference output can be used to rebias capacitorcoupled REF AC REF AC differential or singleended input signals. For the capacitor coupled IN and/or INb inputs, V should be connected to the VT pin and bypassed to REF AC ground with a 0.01 F capacitor. 11 V LVPECL Output Internal 100 Centertapped Termination Pin for IN and IN T 12 IN LVPECL, CML, LVDS Noninverted Differential Input. (Note 2) 13 GND Negative Supply Voltage. 14 V Positive Supply Voltage. CC 15 Q0 LVDS Output Noninverted IN output. Typically loaded with 100 receiver termination resistor across differential pair. 16 Q0 LVDS Output Inverted IN output. Typically loaded with 100 receiver termination resistor across differential pair. EP The Exposed Pad (EP) on the QFN16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heatsinking conduit. The pad is not electrically connected to the die, but is recommended to be electrically and thermally connected to GND on the PC board. 2. In the differential configuration, when the input termination pin (VT) is connected to a termination voltage or left open, and if no signal is applied on IN/IN inputs, then the device will be susceptible to selfoscillation.