NB7L14 2.5V / 3.3V 7GHz/10Gbps Differential 1:4 LVPECL Fanout Buffer MultiLevel Inputs w/ Internal www.onsemi.com Termination MARKING Description DIAGRAM* The NB7L14 is a differential 1:4 LVPECL fanout buffer. The 16 NB7L14 produces four identical LVPECL output copies of Clock or 1 QFN16 NB7L Data operating up to 7 GHz or 10.7 Gb/s, respectively. As such, the MN SUFFIX 14 CASE 485G NB7L14 is ideal for SONET, GigE, Fiber Channel, Backplane and 1 ALYW other Clock or Data distribution applications. The differential inputs incorporate internal 50 termination 16 1 resistors that are accessed through the VT Pin. This feature allows the QFN16 7L14 NB7L14 to accept various logic standards, such as LVPECL, CML, MN SUFFIX ALYW LVDS, LVCMOS or LVTTL logic levels. The V reference REFAC 1 CASE 485AE output can be used to rebias capacitorcoupled differential or singleended input signals. The 1:4 fanout design was optimized for low output skew applications. XXXX = Specific Device Code The NB7L14 is a member of the GigaComm family of high A = Assembly Location performance clock products. L = Wafer Lot Y = Year Features W = Work Week Input Data Rate > 10.7 Gb/s = PbFree Package Input Clock Frequency > 7 GHz (Note: Microdot may be in either location) 165 ps Typical Propagation Delay *For additional marking information, refer to Application Note AND8002/D. 45 ps Typical Rise and Fall Times <15 ps max Output Skew <0.8 ps maximum RMS Clock Jitter Q0 <15 ps pp of Data Dependent Jitter Q0 Differential LVPECL Outputs, 720 mV peaktopeak, typical LVPECL Operating Range: V = 2.375 V to 3.6 V with GND = 0 V CC Q1 IN NECL Operating Range: V = 0 V with GND = 2.375 V to 3.6 V CC 50 Internal Input Termination Resistors, 50 Q1 VT V Reference Output REFAC 50 Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP, IN Q2 EP, and SG Devices Q2 40C to +85C Ambient Operating Temperature V REFAC These are PbFree Devices Q3 Q3 Figure 1. Logic Diagram ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: July, 2015 Rev. 6 NB7L14/DNB7L14 GND Q0 Q0 V Exposed Pad (EP) CC 16 15 14 13 IN 1 12 Q1 VT 2 11 Q1 NB7L14 V 3 10 REFAC Q2 IN 4 9 Q2 56 7 8 GND Q3 Q3 V CC Figure 2. QFN16 Pinout (Top View) Table 1. PIN DESCRIPTION Pin Name I/O Description 1 IN ECL, CML, Noninverted Differential Input. Note 1. Internal 50 Resistor to Termination Pin, VT LVCMOS, LVDS, LVTTL Input 2 VT Internal 50 Termination Pin for IN/IN inputs. 3 VREFAC Output Reference Voltage for capacitorcoupled inputs 4 IN ECL, CML, Inverted Differential Input. Note 1. Internal 50 Resistor to Termination Pin, VT. LVCMOS, LVDS, LVTTL Input 5 GND Negative Supply Voltage 6 Q3 LVPECL Output Inverted Differential Output. Typically Terminated with 50 Resistor to V 2.0 V. CC 7 Q3 LVPECL Output Noninverted Differential Output. Typically Terminated with 50 Resistor to V 2.0 V. CC 8 VCC Positive Supply Voltage 9 Q2 LVPECL Output Inverted Differential Output. Typically Terminated with 50 Resistor to V 2.0 V. CC 10 Q2 LVPECL Output Noninverted Differential Output. Typically Terminated with 50 Resistor to V 2.0 V. CC 11 Q1 LVPECL Output Inverted Differential Output. Typically Terminated with 50 Resistor to V 2.0 V. CC 12 Q1 LVPECL Output Noninverted Differential Output. Typically Terminated with 50 Resistor to V 2.0 V. CC 13 VCC Positive Supply Voltage 14 Q0 LVPECL Output Inverted Differential Output. Typically Terminated with 50 Resistor to V 2.0 V. CC 15 Q0 LVPECL Output Noninverted Differential Output. Typically Terminated with 50 Resistor to V 2.0 V. CC 16 GND Negative Supply Voltage EP The Exposed Pad (EP) on the QFN16 package bottom is thermally connected to the die for im- proved heat transfer out of package. The exposed pad must be attached to a heatsinking con- duit. The pad is electrically connected to the die, and must be electrically connected to device GND. 1. In the differential configuration when the input termination pin (VT) is connected to a common termination voltage or left open, and if no signal is applied on IN/IN input, then, the device will be susceptible to selfoscillation. 2. All VCC and GND pins must be externally connected to a power supply for proper operation. www.onsemi.com 2