Product Specification PE4256 75 SPDT CATV UltraCMOS Switch 5 MHz - 3 GHz Product Description Features The PE4256 is an UltraCMOS Switch designed for CATV 75 characteristic impedance applications, covering a broad frequency range from 5 MHz up to Integrated 75 terminations 3 GHz. This single-supply SPDT switch integrates a two-pin CMOS control interface. It also provides low insertion loss with CTB performance of -90 dBc extremely low bias requirements while operating on a single 3- High isolation 65 dB at 1000 MHz volt supply. In a typical CATV application, the PE4256 provides Low insertion loss: typically 0.5 dB at 5 for a cost effective and manufacturable solution when compared MHz, 0.9 dB at 1000 MHz to mechanical relays. High input IP3: >50 dBm The PE4256 is manufactured on Peregrines UltraCMOS CMOS two-pin control process, a patented variation of silicon-on-insulator (SOI) Single +3 volt supply operation technology on a sapphire substrate, offering the performance Low current consumption: 8 A of GaAs with the economy and integration of conventional Unique all off terminated mode CMOS. 4 x 4 mm QFN package Figure 1. Functional Diagram Peregrine Specification 71-0013-01 Figure 2. Package Type 20-lead 4 x 4 mm QFN Table 1. Electrical Specifications +25 C, V = +3 V (Z = Z = 75 ) DD S L Parameter Condition Minimum Typical Maximum Units 1 Operating Frequency 5 3000 MHz 5-250 MHz 0.5 0.6 250-750 MHz 0.8 0.95 Insertion Loss dB 750-1000 MHz 0.9 1.1 1000-2200 MHz 1.1 1.3 5-250 MHz 75 80 250-750 MHz 65 70 Isolation dB 750-1000 MHz 62 65 1000-2200 MHz 49 52 2 Input IP2 5-1000 MHz 80 dBm 2 Input IP3 5-1000 MHz 50 55 dBm 2 Input 1dB Compression 1000 MHz 29 31 dBm 77 & 110 channels CTB / CSO -90 dBc Power Out = 44 dBm V Switching Time 50% CTRL to 10/90% RF 2 s 3 Video Feedthrough 5-1000 MHz 15 mV pp Notes: 1. Device linearity will begin to degrade below 5 MHz. 2. Measured in a 50 system. 3. Measured with a 1 ns risetime, 0/3 V pulse and 500 MHz bandwidth Document No. 70-0144-04 www.psemi.com 2010-2011 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 8 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: PE4256 Product Specification Figure 3. Pin Configuration (Top View) Table 3. Absolute Maximum Ratings Symbol Parameter/Condition Min Max Unit V Power supply voltage -0.3 4.0 V DD V + DD V Voltage on CTRL input -0.3 V I 0.3 P RF CW power 24 dBm RF T Storage temperature -65 150 C ST T Operating temperature -40 85 C OP ESD voltage V 1000 V ESD (Human Body Model) Exceeding absolute maximum ratings may cause permanent damage. Operation should be restricted to the limits in the Operating Ranges table. Operation between operating range maximum and absolute maximum for extended Table 2. Pin Descriptions periods may reduce reliability. No. Name Description 1 GND Ground Table 4. DC Electrical Specifications 25 C 2 GND Ground 1 Parameter Min Typ Max Unit 3 RF1 RF I/O 4 4 GND Ground V Power Supply 2.7 3.0 3.3 V DD 5 GND Ground I Power Supply Current DD 8 20 A (V = 3 V, V = 3 V) DD CNTL 6 GND Ground 4 Control Voltage High 70% V V 7 GND Ground DD 1 8 RFC Common Control Voltage Low 30% V V DD 4 9 GND Ground 10 GND Ground Electrostatic Discharge (ESD) Precautions 11 GND Ground When handling this UltraCMOS device, observe 4 12 GND Ground the same precautions that you would use with 1 13 RF2 RF I/O other ESD-sensitive devices. Although this device 14 GND Ground contains circuitry to protect it from damage due to 15 GND Ground ESD, precautions should be taken to avoid 2 16 C2 Control 2 exceeding the rating specified. 2 17 C1 Control 1 3 18 VSS/GND Negative Supply Option Moisture Sensitivity Level 19 GND Ground The Moisture Sensitivity Level rating for the 20 VDD Supply PE4256 in the 20-lead 4 x 4 mm QFN Paddle GND Exposed Ground Paddle package is MSL1. Notes: 1. RF pins 3, 8, and 13 must be at 0 VDC. The RF pins do not require DC blocking capacitors for proper operation if the 0 VDC requirement is met. 2. Pins 16 and 17 are the CMOS controls that set the three operating states. 3. Connect pin 18 to GND to enable the on-chip negative voltage generator. Connect pin 18 to V (-3 V) to bypass and disable internal - SS 3 V supply generator. 4. Customer can add external resistance to ground to change or modify termination resistance. 2010-2011 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0144-04 UltraCMOS RFIC Solutions Page 2 of 8 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: