Product Specification PE4259 SPDT High Power UltraCMOS Product Description 10 MHz3.0 GHz RF Switch The PE4259 UltraCMOS RF switch is designed to Features cover a broad range of applications from 10 MHz Single-pin or complementary CMOS through 3000 MHz. This reflective switch integrates logic control inputs on-board CMOS control logic with a low voltage Low insertion loss: CMOS-compatible control interface, and can be controlled using either single-pin or complementary 0.35 dB 1000 MHz control inputs. Using a nominal +3-volt power supply 0.5 dB 2000 MHz voltage, a typical input 1dB compression point of +33.5 dBm can be achieved. Isolation of 30 dB 1000 MHz High ESD tolerance of 2 kV HBM The PE4259 is manufactured on Peregrines UltraCMOS process, a patented variation of silicon- Typical input 1 dB compression point on-insulator (SOI) technology on a sapphire of +33.5 dBm substrate, offering the performance of GaAs with the 1.8V minimum power supply voltage economy and integration of conventional CMOS. Ultra-small SC-70 package Figure 1. Functional Diagram Figure 2. Package Type SC-70 6leadSC70 RFC RF1 RF2 ESD ESD CMOS Control Driver CTRL CTRL or V DD DOC-02109 Document No. DOC-03694-3 www.psemi.com 2005-2016 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 10 ESDPE4259 Product Specification Table 1. Electrical Specifications +25 C, V = 3V (Z = Z = 50 ) DD S L Parameter Condition Minimum Typical Maximum Unit 1 Operation frequency 10 3000 MHz 1000 MHz 0.35 0.45 dB 3 Insertion loss 2000 MHz 0.50 0.60 dB 1000 MHz 29 30 dB Isolation 2000 MHz 19 20 dB 1000 MHz 21 22 dB 3 Return loss 2000 MHz 24 27 dB ON switching time 50% CTRL to 0.1 dB of final value, 1 GHz 1.50 us OFF switching time 50% CTRL to 25 dB isolation, 1 GHz 1.50 us 2 Video feedthrough 15 mV pp 1000 MHz 2.33.3V 31.5 33.5 dBm 1000 MHz 1.82.3V 29.5 30.5 dBm Input 1dB compression point 2500 MHz 2.33.3V 28.5 30.5 dBm 2500 MHz 1.82.3V 28 29 dBm Input IP3 1000 MHz, 20 dBm input power 55 dBm Notes: 1. Device linearity will begin to degrade below 10 MHz. 2. The DC transient at the output of any port of the switch when the control voltage is switched from Low to High or High to Low in a 50 test set-up, measured with 1ns risetime pulses and 500 MHz bandwidth. 3. A tuning capacitor must be added to the application board to optimize the insertion loss and return loss performance. See Figure 6 for details. 2005-2016 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-03694-3 UltraCMOS RFIC Solutions Page 2 of 10