70V07L25JI

70V07S/L HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM Features IDT70V07 easily expands data bus width to 16 bits or more True Dual-Ported memory cells which allow simultaneous using the Master/Slave select when cascading more than access of the same memory location one device High-speed access M/S = VIH for BUSY output flag on Master Commercial: 25/35/55ns (max.) M/S = VIL for BUSY input on Slave Industrial: 35ns (max.) On-chip port arbitration logic Low-power operation Full on-chip hardware support of semaphore signaling IDT70V07S between ports Active: 300mW (typ.) Fully asynchronous operation from either port Standby: 3.3mW (typ.) TTL-compatible, single 3.3V (0.3V) power supply IDT70V07L Available in 68-pin PGA and a 80-pin TQFP Active: 300mW (typ.) Industrial temperature range (-40C to +85C) is available Standby: 660W (typ.) for selected speeds Interrupt Flag Green parts available, see ordering information Functional Block Diagram OER OEL CER CEL R/WR R/WL I/O0L-I/O7L I/O0R-I/O7R I/O I/O Control Control , (1,2) (1,2) BUSYL BUSYR A14R A14L Address MEMORY Address Decoder ARRAY Decoder A0L A0R 15 15 ARBITRATION CEL INTERRUPT CER SEMAPHORE OEL OER LOGIC R/WR R/WL SEML SEMR M/S (2) (2) INTR INTL 2943 drw 01 NOTES: 1. (MASTER): BUSY is output (SLAVE): BUSY is input. 2. BUSY and INT outputs are non-tri-stated push-pull. JULY 2019 1 DSC 2943/1170V07S/L High-Speed 32K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges address, and I/O pins that permit independent, asynchronous access for Description reads or writes to any location in memory. An automatic power down The IDT70V07 is a high-speed 32K x 8 Dual-Port Static RAM. The feature controlled by CE permits the on-chip circuitry of each port to enter IDT70V07 is designed to be used as a stand-alone 256K-bit Dual-Port a very low standby power mode. RAM or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit- Fabricated using CMOS high-performance technology, these devices or-more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM typically operate on only 300mW of power. approach in 16-bit or wider memory system applications results in full- The IDT70V07 is packaged in a ceramic 68-pin PGA and a 80-pin speed, error-free operation without the need for additional discrete logic. thin quad flatpack (TQFP). This device provides two independent ports with separate control, (1,2,3) Pin Configurations 10/25/01 INDEX 98 76 5 4 3 21 68676665 64 63 62 61 60 I/O2L A5L 10 59 I/O3L A4L 11 I/O4L 58 A3L 12 57 I/O5L 13 A2L 56 GND 14 A1L 55 I/O6L 15 A0L IDT70V07J (4) 54 I/O7L INTL 16 J68-1 VCC 53 BUSYL 17 68-Pin PLCC 52 GND 18 GND (5) Top View 51 I/O0R 19 M/S 50 I/O1R BUSYR 20 49 I/O2R INTR 21 48 VCC 22 A0R I/O3R 47 23 A1R 46 I/O4R 24 A2R 45 I/O5R 25 A3R 44 I/O6R A4R 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 2943 drw 02 NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground. 3. J68-1 package body is approximately .95 in x .95 in x .17 in. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. 2 I/O7R I/O1L N/C I/O0L OER N/C R/WR OEL SEMR R/WL CER SEML A14R CEL A13R A14L GND A13L A12R VCC A11R A12L A10R A11L A9R A10L A8R A9L A7R A8L A6R A7L A5R A6L