70V08L20PFGI

70V08L HIGH-SPEED 3.3V 64K x 8 DUAL-PORT STATIC RAM Features True Dual-Ported memory cells which allow simultaneous M/S = VIH for BUSY output flag on Master, access of the same memory location M/S = VIL for BUSY input on Slave High-speed access Busy and Interrupt Flags Commercial: 15ns (max.) On-chip port arbitration logic Industrial: 20ns (max.) Full on-chip hardware support of semaphore signaling Low-power operation between ports IDT70V08L Fully asynchronous operation from either port Active: 550mW (typ.) LVTTL-compatible, single 3.3V (0.3V) power supply Standby: 1mW (typ.) Available in a 100-pin TQFP Dual chip enables allow for depth expansion without Industrial temperature range (40C to +85C) is available external logic for selected speeds IDT70V08 easily expands data bus width to 16 bits or Green parts available, see ordering information more using the Master/Slave select when cascading more than one device Functional Block Diagram R/W L R/W R CE0L CE0R CE1L CE1R OE OER L I/O I/O 0-7L I/O 0-7R I/O Control Control (1,2) (1,2) BUSYL BUSYR 64Kx8 A15L A15R MEMORY Address Address ARRAY Decoder Decoder A0L A 0R 70V08 A 15L A 15R A 0L A ARBITRATION 0R CE 0L INTERRUPT CE 0R SEMAPHORE CE1L CE 1R LOGIC OE L OE R R/W L R/W R SEML SEMR (2) (2) L INT INT R (1) M/S 3740 drw 01 NOTES: 1. BUSY is an input as a Slave (M/S-VIL) and an output when it is a Master (M/S-VIH). 2. BUSY and INT are non-tri-state totem-pole outputs (push-pull). MAY 2019 1 DSC-3740/1170V08L High-Speed 3.3.V 64K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Description The IDT70V08 is a high-speed 64K x 8 Dual-Port Static RAM. The for reads or writes to any location in memory. An automatic power IDT70V08 is designed to be used as a stand-alone 512K-bit Dual-Port down feature controlled by the chip enables (either CE0 or CE1) RAM or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit- permit the on-chip circuitry of each port to enter a very low standby or-more word system. Using the IDT MASTER/SLAVE Dual-Port power mode. RAM approach in 16-bit or wider memory system applications results Fabricated using CMOS high-performance technology, in full-speed, error-free operation without the need for additional these devices typically operate on only 550mW of power. discrete logic. The IDT70V08 is packaged in a 100-pin Thin Quad Flatpack This device provides two independent ports with separate control, (TQFP). address, and I/O pins that permit independent, asynchronous access (1,2,3) Pin Configurations 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC NC 50 76 49 NC NC 77 NC A6R 48 78 47 I/O7R A5R 79 46 80 A4R I/O6R 45 81 I/O5R A3R 82 44 I/O4R A2R 83 43 I/O3R A1R A0R 84 42 VDD INTR 41 I/O2R 85 40 BUSYR 70V08 I/O1R 86 (4) PNG100 39 I/O0R M/S 87 Vss 38 88 Vss 100-Pin BUSYL 89 37 VDD TQFP 36 INTL 90 I/O0L Top View NC 91 35 I/O1L 34 A0L 92 Vss 93 33 I/O2L A1L I/O3L A2L 94 32 A3L 95 31 I/O4L 96 A4L 30 I/O5L 29 A5L 97 I/O6L 98 A6L 28 I/O7L NC 99 27 NC NC 100 26 Vss 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 3740 drw 02 NOTES: 1. All Vcc pins must be connected to power supply. 2. All GND pins must be connected to ground. 3. Package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 2 NC NC NC NC A7L A7R A8L A8R A9L A9R A10L A10R A11L A11R A12L A12R A13L A13R A14L A14R A15L A15R NC NC VDD Vss NC NC NC NC NC NC NC NC CE0L CE0R CE1L CE1R SEML SEMR R/WL R/WR OEL OER Vss Vss NC Vss NC NC