WRITE CONTROL WRITE FLAGS 3.3V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION IDT72V51233 589,824 bits IDT72V51243 1,179,648 bits IDT72V51253 2,359,296 bits Individual, Active queue flags (OV, FF, PAE, PAF) FEATURES: 4 bit parallel flag status on both read and write ports Choose from among the following memory density options: Provides continuous PAE and PAF status of up to 4 Queues IDT72V51233 Total Available Memory = 589,824 bits Global Bus Matching - (All Queues have same Input Bus Width IDT72V51243 Total Available Memory = 1,179,648 bits and Output Bus Width) IDT72V51253 Total Available Memory = 2,359,296 bits User Selectable Bus Matching Options: Configurable from 1 to 4 Queues - x18in to x18out Queues may be configured at master reset from the pool of - x9in to x18out Total Available Memory in blocks of 512 x 18 or 1,024 x 9 - x18in to x9out Independent Read and Write access per queue - x9in to x9out User programmable via serial port FWFT mode of operation on read port Default multi-queue device configurations Partial Reset, clears data in single Queue -IDT72V51233: 8,192 x 18 x 4Q or 16,384 x 9 x 4Q Expansion of up to 8 multi-queue devices in parallel is available -IDT72V51243: 16,384 x 18 x 4Q or 32,768 x 9 x 4Q JTAG Functionality (Boundary Scan) -IDT72V51253: 32,768 x 18 x 4Q or 65,536 x 9 x 4Q Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm 100% Bus Utilization, Read and Write on every clock cycle HIGH Performance submicron CMOS technology 166 MHz High speed operation (6ns cycle time) Industrial temperature range (-40C to +85C) is available 3.7ns access time FUNCTIONAL BLOCK DIAGRAM MULTI-QUEUE FLOW-CONTROL DEVICE WADEN RADEN FSTR ESTR Q0 WRADD RDADD 5 6 WEN REN WCLK RCLK OE Q D out in x9, x18 x9, x18 DATA OUT DATA IN OV FF Q3 PAF PAE PAFn 4 PAEn 4 5941 drw01 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES FEBRUARY 2009 1 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-5941/10 READ FLAGS READ CONTROLCOMMERCIAL AND INDUSTRIAL IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES TEMPERATURE RANGES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits Bus Matching is available on this device, either port can be 9 bits or 18 bits DESCRIPTION: wide. When Bus Matching is used the device ensures the logical transfer of data The IDT72V51233/72V51243/72V51253 multi-queue flow-control de- throughput in a Little Endian manner. vices are single chip within which anywhere between 1 and 4 discrete FIFO The user has full flexibility configuring queues within the device, being able queues can be setup. All queues within the device have a common data input to program the total number of queues between 1 and 4, the individual queue bus, (write port) and a common data output bus, (read port). Data written into depths being independent of each other. The programmable flag positions are the write port is directed to a respective queue via an internal de-multiplex also user programmable. All programming is done via a dedicated serial port. operation, addressed by the user. Data read from the read port is accessed If the user does not wish to program the multi-queue device, a default option is from a respective queue via an internal multiplex operation, addressed by available that configures the device in a predetermined manner. the user. Data writes and reads can be performed at high speeds up to Both Master Reset and Partial Reset pins are provided on this device. A Master 166MHz, with access times of 3.7ns. Data write and read operations are totally Reset latches in all configuration setup pins and must be performed before independent of each other, a queue maybe selected on the write port and programming of the device can take place. A Partial Reset will reset the read and a different queue on the read port or both ports may select the same queue write pointers of an individual queue, provided that the queue is selected on both simultaneously. the write port and read port at the time of partial reset. The device provides Full flag and Output Valid flag status for the queue A JTAG test port is provided, here the multi-queue flow-control device has a selected for write and read operations respectively. Also a Programmable fully functional Boundary Scan feature, compliant with IEEE 1149.1 Standard Almost Full and Programmable Almost Empty flag for each queue is provided. Test Access Port and Boundary Scan Architecture. Two 4 bit programmable flag busses are available, providing status of all See Figure 1, Multi-Queue Flow-Control Device Block Diagram for an outline queues, including queues not selected for write or read operations, these flag of the functional blocks within the device. busses provide an individual flag per queue. 2