WRITE CONTROL WRITE FLAGS 3.3V MULTI-QUEUE FLOW-CONTROL DEVICES (16 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits IDT72V51436 1,179,648 bits IDT72V51446 2,359,296 bits IDT72V51456 Shows PAE and PAF status of 8 Queues FEATURES: Direct or polled operation of flag status bus Choose from among the following memory density options: Global Bus Matching - (All Queues have same Input Bus Width IDT72V51436 Total Available Memory = 589,824 bits and Output Bus Width) IDT72V51446 Total Available Memory = 1,179,648 bits User Selectable Bus Matching Options: IDT72V51456 Total Available Memory = 2,359,296 bits x36in to x36out Configurable from 1 to 16 Queues x18in to x36out Queues may be configured at master reset from the pool of x9in to x36out Total Available Memory in blocks of 256 x 36 x36in to x18out Independent Read and Write access per queue x36in to x9out User programmable via serial port FWFT mode of operation on read port Default multi-queue device configurations Packet mode operation IDT72V51436 : 1,024 x 36 x 16Q Partial Reset, clears data in single Queue IDT72V51446 : 2,048 x 36 x 16Q Expansion of up to 8 multi-queue devices in parallel is available IDT72V51456 : 4,096 x 36 x 16Q JTAG Functionality (Boundary Scan) 100% Bus Utilization, Read and Write on every clock cycle Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm 166 MHz High speed operation (6ns cycle time) HIGH Performance submicron CMOS technology 3.7ns access time Industrial temperature range (-40C to +85C) is available Individual, Active queue flags (OV, FF, PAE, PAF, PR) 8 bit parallel flag status on both read and write ports FUNCTIONAL BLOCK DIAGRAM MULTI-QUEUE FLOW-CONTROL DEVICE Q0 WADEN RADEN FSTR ESTR WRADD RDADD Q1 7 8 WEN REN WCLK RCLK Q2 OE Q out D in x36 x36 DATA OUT DATA IN OV FF PR PAF PAE Q15 PAFn 8 PAEn/PRn 8 5935 drw01 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc JUNE 2003 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 1 DSC-5935/9 READ FLAGS READ CONTROLIDT72V51436/72V51446/72V51456 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES COMMERCIAL AND INDUSTRIAL (16 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits TEMPERATURE RANGES A Packet mode of operation is also provided when the device is configured DESCRIPTION: for 36 bit input and 36 bit output port sizes. The Packet mode provides the user The IDT72V51436/72V51446/72V51456 multi-queue flow-control de- with a flag output indicating when at least one (or more) packets of data within a vices are single chip within which anywhere between 1 and 16 discrete FIFO queue is available for reading. The Packet Ready provides the user with a means queues can be setup. All queues within the device have a common data input by which to mark the start and end of packets of data being passed through the bus, (write port) and a common data output bus, (read port). Data written into queues. The multi-queue device then provides the user with an internally the write port is directed to a respective queue via an internal de-multiplex generated packet ready status per queue. operation, addressed by the user. Data read from the read port is accessed The user has full flexibility configuring queues within the device, being able from a respective queue via an internal multiplex operation, addressed by the to program the total number of queues between 1 and 16, the individual queue user. Data writes and reads can be performed at high speeds up to 166MHz, depths being independent of each other. The programmable flag positions are with access times of 3.7ns. Data write and read operations are totally also user programmable. All programming is done via a dedicated serial port. independent of each other, a queue maybe selected on the write port and a If the user does not wish to program the multi-queue device, a default option is different queue on the read port or both ports may select the same queue available that configures the device in a predetermined manner. simultaneously. Both Master Reset and Partial Reset pins are provided on this device. A Master The device provides Full flag and Output Valid flag status for the queue Reset latches in all configuration setup pins and must be performed before selected for write and read operations respectively. Also a Programmable programming of the device can take place. A Partial Reset will reset the read and Almost Full and Programmable Almost Empty flag for each queue is provided. write pointers of an individual queue, provided that the queue is selected on both Two 8 bit programmable flag busses are available, providing status of queues the write port and read port at the time of partial reset. not selected for write or read operations. When 8 or less queues are configured A JTAG test port is provided, here the multi-queue flow-control device has a in the device these flag busses provide an individual flag per queue, when fully functional Boundary Scan feature, compliant with IEEE 1149.1 Standard more than 8 queues are used, either a Polled or Direct mode of bus operation Test Access Port and Boundary Scan Architecture. provides the flag busses with all queues status. See Figure 1, Multi-Queue Flow-Control Device Block Diagram for an outline Bus Matching is available on this device, either port can be 9 bits, 18 bits of the functional blocks within the device. or 36 bits wide provided that at least one port is 36 bits wide. When Bus Matching is used the device ensures the logical transfer of data throughput in a Little Endian manner. 2