IDT74FCT388915T 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE) COMMERCIAL TEMPERATURE RANGE 3.3V LOW SKEW PLL-BASED IDT74FCT388915T CMOS CLOCK DRIVER 70/100/133/150 (WITH 3-STATE) PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016 FEATURES: DESCRIPTION: 0.5 MICRON CMOS Technology The FCT388915T uses phase-lock loop technology to lock the fre- Input frequency range: 10MHz f2Q Max. spec quency and phase of outputs to the input reference clock. It provides low (FREQ SEL = HIGH) skew clock distribution for high performance PCs and workstations. One Max. output frequency: 150MHz of the outputs is fed back to the PLL at the FEEDBACK input resulting Pin and function compatible with FCT88915T, MC88915T in essentially zero delay across the device. The PLL consists of the 5 non-inverting outputs, one inverting output, one 2x output, one phase/frequency detector, charge pump, loop lter and VCO. The VCO 2 output all outputs are TTL-compatible is designed for a 2Q operating frequency range of 40MHz to f2Q Max. 3-State outputs The FCT388915T provides 8 outputs, the Q5 output is inverted from Duty cycle distortion < 500ps (max.) the Q outputs. The 2Q runs at twice the Q frequency and Q/2 runs at 32/16mA drive at CMOS output voltage levels half the Q frequency. VCC = 3.3V 0.3V The FREQ SEL control provides an additional 2 option in the Inputs can be driven by 3.3V or 5V components output path. PLL EN allows bypassing of the PLL, which is useful in Available in 28 pin PLCC and SSOP packages static test modes. When PLL EN is low, SYNC input may be used as NOT RECOMMENDED FOR NEW DESIGNS a test clock. In this test mode, the input frequency is not limited to the For functional replacement use 8T49N286A speci ed range and the polarity of outputs is complementary to that in normal operation (PLL EN = 1). The LOCK output attains logic HIGH when the PLL is in steady-state phase and frequency lock. When OE/ RST is low, all the outputs are put in high impedance state and registers at Q, Q and Q/2 outputs are reset. The FCT388915T requires one external loop lter component as recommended in Figure 3. FUNCTIONAL BLOCK DIAGRAM The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE MARCH 2016 1 DSC-4243/7IDT74FCT388915T 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE) COMMERCIAL TEMPERATURE RANGE PIN CONFIGURATION SSOP PLCC TOP VIEW TOP VIEW PIN DESCRIPTION Pin Name I/O Description SYNC(0) I Reference clock input SYNC(1) I Reference clock input REF SEL I Chooses reference between SYNC (0) & SYNC (1) (refer to functional block diagram) FREQ SEL I Selects between 1 and 2 frequency options (refer to functional block diagram) FEEDBACK I Feedback input to phase detector LF I Input for external loop lter connection Q0-Q4 O Clock output Q5 O Inverted clock output 2Q O Clock output (2 x Q frequency) Q/2 O Clock output (Q frequency 2) LOCK O Indicates phase lock has been achieved (HIGH when locked) OE/RST I Asynchronous reset (active LOW) and output enable (active HIGH). When HIGH, outputs are enabled. When LOW, outputs are in HIGH impedance. PLL EN I Disables phase-lock for low frequency testing (refer to functional block diagram) 2