Product Information

83023AMILFT

83023AMILFT electronic component of Renesas

Datasheet
Dual,1-to-1 Differential-to-LVCMOS Translator/Buffer

Manufacturer: Renesas
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)
N/A

Obsolete
Availability Price Quantity
0 - WHS 1

MOQ : 3000
Multiples : 3000

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83023AMILFT
Renesas

3000 : USD 3.3988
6000 : USD 3.2624
12000 : USD 2.9893
18000 : USD 2.8529
30000 : USD 2.7164
N/A

Obsolete
0 - WHS 2

MOQ : 1
Multiples : 1

Stock Image

83023AMILFT
Renesas

1 : USD 5.2545
10 : USD 3.4693
25 : USD 3.2829
100 : USD 2.9204
250 : USD 2.7755
500 : USD 2.558
1000 : USD 2.1955
3000 : USD 2.1955
6000 : USD 2.1541
N/A

Obsolete
     
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RoHS - XON
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Dual, 1-TO-1 83023I Data Sheet Differential-to-LVCMOS Translator/Buffer GENERAL DESCRIPTION Features The 83023I is a dual, 1-to-1 Differential-to-LVCMOS Two LVCMOS / LVTTL outputs Translator/Fanout Buffer. The differential inputs can accept most Two differential CLKx, nCLKx input pairs differential signal types (LVDS, LVHSTL, LVPECL, SSTL, and HCSL) and translate into two single-ended LVCMOS outputs. CLK, nCLK pairs can accept the following differential The small 8-lead SOIC footprint makes this device ideal for use input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL in applications with limited board space. Maximum output frequency: 350MHz (typical) Output skew: 60ps (maximum) Part-to-part skew: 500ps (maximum) Additive phase jitter, RMS: 0.14ps (typical) Small 8 lead SOIC package saves board space 3.3V operating supply -40C to 85C ambient operating temperature BLOCK DIAGRAM PIN ASSIGNMENT CLK0 Q0 CLK0 VDD 1 8 nCLK0 nCLK0 2 7 Q0 nCLK1 3 6 Q1 CLK1 CLK1 4 5 GND Q1 nCLK1 83023I 8-Lead SOIC 3.8mm x 4.8mm x 1.47mm package body M Package Top View 2015 Integrated Device Technology, Inc 1 December 14, 201583023I Data Sheet TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1 CLK0 Input Pulldown Non-inverting differential clock input. 2 nCLK0 Input Pullup Inverting differential clock input. 3 nCLK1 Input Pullup Inverting differential clock input. 4 CLK1 Input Pulldown Non-inverting differential clock input. 5 GND Power Power supply ground. 6 Q1 Output Single clock output. LVCMOS / LVTTL interface levels. 7 Q0 Output Single clock output. LVCMOS / LVTTL interface levels. 8V Power Positive supply pin. DD NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN Power Dissipation Capacitance C 23 pF V = 3.6V PD (per output) DD R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN R Output Impedance 7 OUT 2015 Integrated Device Technology, Inc 2 December 14, 2015

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
CEL (RENESAS)
ID4
IDT
IDT, Integrated Device Technology Inc
INTEGRATED DEVICE
INTEGRATED DEVICE TECHNOLOGY
INTEGRATED DEVICES TECH AID
Intersil
INTERSIL - FGC
Intersil(Renes as Electronics)
Intersil(Renesas Electronics)
ITS
REA
RENESAS
RENESAS (IDT)
RENESAS (INTERSIL)
Renesas / IDT
Renesas / Intersil
Renesas Electronics
Renesas Electronics America
RENESAS TECHNOLOGY

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