Low Skew, 1-to-8 Differential/LVCMOS-to- 8308I Data Sheet LVCMOS Fanout Buffer GENERAL DESCRIPTION FEATURES The 8308I is a low-skew, 1-to-8 Fanout Buffer. The 8308I has two Eight LVCMOS/LVTTL outputs, (7 typical output impedance) selectable clock inputs. The CLK, nCLK pair can accept most Selectable LVCMOS CLK or differential CLK, nCLK inputs differential input levels. The LVCMOS CLK can accept LVCMOS or LVTTL input levels. The low impedance LVCMOS/LVTTL outputs CLK, nCLK pair can accept the following differential are designed to drive 50 series or parallel terminated transmission input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL lines. The effective fanout can be increased from 8 to 16 by utilizing Maximum Output Frequency: 350MHz the ability of the outputs to drive two series terminated transmission lines. Output Skew: (3.3V 5%): 100ps (maximum) Part to Part Skew: (3.3V 5%): 1ns (maximum) The 8308I is characterized for 3.3V core/3.3V output, 3.3V core/2.5V output or 2.5V core/2.5V output operation. Supply Voltage Modes: Guaranteed output and part-part skew characteristics make the (Core/Output) 8308I ideal for those clock distribution applications requiring well 3.3V/3.3V de ned performance and repeatability. 3.3V/2.5V 2.5V/2.5V -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package BLOCK DIAGRAM PIN ASSIGNMENT Pullup CLK EN Q0 24 VDDO D 1 GND 2 23 Q2 Q CLK SEL GND 3 22 LE Pullup LVCMOS CLK LVCMOS CLK 4 Q3 21 1 CLK VDDO Q0 5 20 Pullup CLK nCLK 6 Q4 19 0 Pulldown nCLK CLK EN 7 GND 18 Q1 OE Q5 8 17 VDD 9 VDDO Pullup 16 Q2 CLK SEL GND 10 Q6 15 Q1 GND 11 14 Q3 VDDO 12 Q7 13 Q4 8308I Q5 24-Lead, 173-MIL TSSOP 4.4mm x 7.8mm x 0.925mm body package Q6 G Package Q7 Top View Pullup OE 2015 Integrated Device Technology, Inc 1 December 10, 20158308I Data Sheet TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 11, 13, 15, Q0, Q1, Q7, Q6, Output Clock outputs. LVCMOS / LVTTL interface levels. 17, 19, 21, 23 Q5, Q4,Q3, Q2 2, 10, 14, 18, 22 GND Power Power supply ground. Clock select input. Selects LVCMOS clock input when HIGH. 3 CLK SEL Input Pullup Selects CLK, nCLK inputs when LOW. See Table 3A. LVCMOS / LVTTL interface levels. 4 LVCMOS CLK Input Pullup Clock input. LVCMOS / LVTTL interface levels. 5 CLK Input Pullup Non-inverting differential clock input. 6 nCLK Input Pulldown Inverting differential clock input. 7 CLK EN Input Pullup Clock enable. LVCMOS / LVTTL interface levels. Output enable. LVCMOS / LVTTL interface levels. 8 OE Input Pullup See Table 3B. 9V Power Power supply pin. DD 12, 16, 20, 24 V Power Output supply pins. DDO NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4pF IN Power Dissipation Capacitance C 12 pF PD (per output) R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN R Output Impedance 5 7 12 OUT TABLE 3A. CLOCK SELECT FUNCTION TABLE TABLE 3B. OE SELECT FUNCTION TABLE Control Input Control Input Clock Input Output Operation CLK SEL OE 0 CLK, nCLK is selected 0 Outputs Q0:Q7 are in Hi-Z (disabled) 1 LVCMOS CLK is selected 1 Outputs Q0:Q7 are active (enabled) TABLE 3C. CLOCK INPUT FUNCTION TABLE Inputs Outputs Input to Output Mode Polarity CLK SEL LVCMOS CLK CLK nCLK Q0:Q7 0 0 1 LOW Differential to Single Ended Non Inverting 0 1 0 HIGH Differential to Single Ended Non Inverting 0 0 Biased NOTE 1 LOW Single Ended to Single Ended Non Inverting 0 1 Biased NOTE 1 HIGH Single Ended to Single Ended Non Inverting 0 Biased NOTE 1 0 HIGH Single Ended to Single Ended Inverting 0 Biased NOTE 1 1 LOW Single Ended to Single Ended Inverting 1 0 LOW Single Ended to Single Ended Non Inverting 1 1 HIGH Single Ended to Single Ended Non Inverting NOTE 1: Please refer to the Application Information section, Wiring the Differential Input to Accept Single Ended Levels. 2015 Integrated Device Technology, Inc 2 December 10, 2015