GND GND Q2 Q7 Q1 Q8 VDD VDD VDD VDD Q0 Q9 GND GND GND GND Low Skew, 1-to-10, HSTL Fanout Buffer 83210 Data Sheet GENERAL DESCRIPTION FEATURES The 83210 is a low skew, 1-to-10 HSTL Fanout Buffer. Ten single-ended HSTL outputs The class II HSTL outputs are balanced push-pull in design, capable One single-ended HSTL clock input of delivering 16mA into a 10pF load. This class allows both source series termination and symmetrically double parallel termination. Maximum input frequency: 150MHz Output skew: 110ps (maximum) Part-to-part skew: 2ns (maximum) 1.5V power supply 0C to 85C ambient operating temperature Available in lead-free (RoHS 6) package BLOCK DIAGRAM PIN ASSIGNMENT Q0 32 31 30 29 28 27 26 25 Q1 VDD GND 1 24 GND Q3 2 23 IN VDD Q4 3 22 nOE VDD 4 21 ICS83210 Q8 GND VDD 5 20 IN Q5 6 19 Q9 VDD Q6 7 18 Pulldown nOE GND GND 8 17 9 10 11 12 13 14 15 16 32-Lead TQFP 7mm x 7mm x 1.0mm package body Y package Top View 2016 Integrated Device Technology, Inc 1 Revision A March 10, 201683210 Data Sheet TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 3, 7, 12, 13, V Power Power supply pins. DD 20, 21, 28, 29 2, 5, 8, 9, 10, GND Power Power supply ground. 16, 17, 24, 25, 31, 32 Output enable/disable input pin. When LOW, outputs Qx outputs are 4 nOE Input Pulldown enabled. When HIGH, Qx outputs are disabled low. LVCMOS/LVTTL interface levels. 5 IN Input Single-ended reference clock input. HSTL interface levels. 11, 14, 15, Q9, Q8, Q7, Q6, 18, 19, 22, Q5, Q4, Q3, Q2, Output Single-ended HSTL clock outputs. 23, 26, 27, 30 Q1, Q0 NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4pF IN R Input Pulldown Resistor 51 k PULLDOWN C Output Pin Capacitance 4.5 6 pF OUT R Output Impedance 20 OUT 2016 Integrated Device Technology, Inc 2 Revision A March 10, 2016