GND Q5 Q4 Q3 VDDO Q2 Q1 Q0 Low Skew, 1-to-18 83940I-01 LVPECL-to-LVCMOS/LVTTL Fanout DATA SHEET General Description Features The 83940I-01 is a low skew, 1-to-18 LVPECL-to-LVCMOS/ LVTTL Eighteen LVCMOS/LVTTL outputs, 23 typical output impedance Fanout Buffer. The 83940I-01 has two selectable clock inputs. The Selectable LVCMOS CLK or LVPECL clock inputs PCLK, nPCLK pair can accept LVPECL or SSTL input levels. The PCLK, nPCLK pair can accept the following differential input single-ended clock input accepts LVCMOS or LVTTL input levels. levels: LVPECL, SSTL The 83940I-01 is characterized at full 3.3V, full 2.5V and mixed 3.3V LVCMOS CLK supports the following input types: LVCMOS or input and 2.5V output operating supply modes. Guaranteed output LVTTL and part-to-part skew characteristics make the 83940I-01 ideal for Maximum output frequency: 175MHz those clock distribution applications demanding well defined Additive phase jitter, RMS: 0.108ps (typical), 3.3V/3.3V performance and repeatability. Output skew: 115ps (maximum) Part-to-part skew: 800ps (maximum), 3.3V/3.3V Operating supply modes: Core/Output 3.3V/3.3V 3.3V/2.5V 2.5V/2.5V -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Pin Assignment Block Diagram Pulldown CLK SEL Pulldown PCLK 32 31 30 29 28 27 26 25 Pullup/Pulldown 0 nPCLK 18 GND 1 24 Q6 Q 0:17 GND 2 23 Q7 Pulldown LVCMOS CLK LVCMOS CLK 3 22 Q8 1 ICS83940I-01 CLK SEL 4 21 VDDO PCLK 5 20 Q9 nPCLK 6 19 Q10 VDD 7 18 Q11 VDDO 8 GND 17 9 10 11 12 13 14 15 16 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View 83940I-01 Rev A 3/27/15 1 2015 Integrated Device Technology, Inc. Q17 Q16 Q15 GND Q14 Q13 Q12 VDDO83940I-01 DATA SHEET Table 1. Pin Descriptions Number Name Type Description 1, 2, 12, 17, 25 GND Power Power supply ground. 3 LVCMOS CLK Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. Clock select input. When HIGH, selects LVCMOS CLK input. When LOW, 4 CLK SEL Input Pulldown selects PCLK, nPCLK inputs. LVCMOS / LVTTL interface levels. 5 PCLK Input Pulldown Non-inverting differential LVPECL clock input. Pullup/ 6 nPCLK Input Inverting differential LVPECL clock input. V /2 default when left floating. DD Pulldown 7V Power Power supply pin. DD 8, 16, 21, 29 V Power Output supply pins. DDO 9, 10, 11, Q17, Q16, Q15, 13, 14, 15, Q14, Q13, Q12, 18, 19, 20, Q11, Q10, Q9, Output Single-ended clock outputs. LVCMOS/LVTTL interface levels. 22, 23, 24, Q8, Q7, Q6, 26, 27, 28, Q5, Q4, Q3, 30, 31, 32 Q2, Q1, Q0 NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4pF IN R Input Pulldown Resistor 51 k PULLDOWN R Input Pullup Resistor 51 k PULLUP Power Dissipation Capacitance C 9pF PD (per output) R Output Impedance 17 23 28 OUT Rev A 3/27/15 2 LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER