Low Skew, 1-to-2, Differential-to-2.5V, 3.3V ICS853S011CI LVPECL/ECL Fanout Buffer DATA SHEET General Description Features The ICS853S011CI is a low skew, high performance 1-to-2 Two differential 2.5V, 3.3V LVPECL/ECL outputs Differential-to-2.5V/3.3V LVPECL/ECL Fanout Buffer. The One differential PCLK, nPCLK input pair ICS853S011CI is characterized to operate from either a 2.5V or a PCLK, nPCLK pairs can accept the following 3.3V power supply. Guaranteed output and part-to-part skew differential input levels: LVPECL, LVDS, CML, SSTL characteristics make the ICS853S011CI ideal for those clock Maximum output frequency: >2.5GHz distribution applications demanding well defined performance and Translates any single-ended input signal to 3.3V LVPECL levels repeatability. with resistor bias on nPCLK input Output skew: 20ps (maximum) Part-to-part skew: 150ps (maximum) Propagation delay: 330ps (maximum) LVPECL mode operating voltage supply range: V = 2.375V to 3.8V, V = 0V CC EE ECL mode operating voltage supply range: V = 0V, V = -3.8V to -2.375V CC EE -40C to 85C ambient operating temperature Lead-free (RoHS 6) packaging Block Diagram Pin Assignment Pulldown Q0 PCLK VCC Q0 1 8 Pullup/Pulldown PCLK nPCLK nQ0 nQ0 2 7 Q1 3 6 nPCLK Q1 VEE nQ1 4 5 nQ1 ICS853S011CI 8-Lead SOIC, 150MIL 3.90mm x 4.90mm x 1.37mm package body M Package Top View 8-Lead TSSOP, 118MIL 3.0mm x 3.0mm x 0.97mm package body G Package Top View ICS853S011CGI REVISION A JULY 16, 2013 1 2013 Integrated Device Technology, Inc.ICS853S011CI Data Sheet LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER Pin Description and Pin Characteristic Tables Table 1. Pin Descriptions Number Name Type Description 1, 2 Output Differential output pair. LVPECL/ECL interface levels. Q0, nQ0 3, 4 Output Differential output pair. LVPECL/ECL interface levels. Q1, nQ1 5V Power Negative supply pin. EE Pullup/ 2 6nPCLK Input Inverting differential LVPECL clock input. When left floating, defaults to / V . 3 CC Pulldown 7 PCLK Input Pulldown Non-inverting differential LVPECL clock input. 8V Power Positive supply pin. CC NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units R Input Pulldown Resistor 75 k PULLDOWN R Pullup Resistors 37 k PULLUP ICS853S011CGI REVISION A JULY 16, 2013 2 2013 Integrated Device Technology, Inc.