PCLK0 Low Skew, 1-to-5, Differential-to-2.5V, 3.3V ICS853S014I LVPECL/ECL Fanout Buffer DATA SHEET General Description Features The ICS853S014I is a low skew, high performance 1-to-5, 2.5V/3.3V Five differential LVPECL/ECL outputs Differential-to-LVPECL/ECL Fanout Buffer. The ICS853S014I has Two selectable differential LVPECL clock inputs two selectable clock inputs. PCLKx, nPCLKx pairs can accept the following Guaranteed output and part-to-part skew characteristics make the ICS853S014I ideal for those applications demanding well defined differential input levels: LVPECL, LVDS, CML, SSTL performance and repeatability. Maximum output frequency: 2GHz Output skew: 55ps (maximum) Part-to-part skew: 100ps (maximum) Propagation delay: 500ps (maximum) Additive phase jitter, RMS: 0.10ps (maximum) LVPECL mode operating voltage supply range: V = 2.375V to 3.8V, V = 0V CC EE ECL mode operating voltage supply range: V = 0V, V = -3.8V to -2.375V CC EE -40C to 85C ambient operating temperature Lead-free (RoHS 6) packaging Block Diagram Pin Assignment Pulldown nEN D Q0 1 20 VCC Q nQ0 2 19 nEN Pulldown PCLK0 CLK Q1 3 18 VCC 0 Pullup/Pulldown nQ1 4 17 nPCLK1 nPCLK0 Q0 Q2 5 16 PCLK1 Pulldown PCLK1 nQ0 nQ2 6 15 VBB 1 Pullup/Pulldown Q3 7 14 nPCLK0 nPCLK1 Q1 nQ3 8 13 nQ1 Q4 9 12 CLK SEL Pulldown CLK SEL nQ4 10 11 VEE Q2 V BB nQ2 ICS853S014I Q3 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body nQ3 G Package Q4 Top View nQ4 ICS853S014AGI REVISION D MAY 23, 2013 1 2013 Integrated Device Technology, Inc.ICS853S014I Data Sheet LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER Pin Description and Pin Characteristic Table Table 1. Pin Descriptions Number Name Type Description 1, 2 Output Differential output pair. LVPECL/ECL interface levels. Q0, nQ0 3, 4 Output Differential output pair. LVPECL/ECL interface levels. Q1, nQ1 5, 6 Q2, nQ2 Output Differential output pair. LVPECL/ECL interface levels. 7, 8 Output Differential output pair. LVPECL/ECL interface levels. Q3, nQ3 9, 10 Output Differential output pair. LVPECL/ECL interface levels. Q4, nQ4 11 V Power Negative supply pin. EE Clock select input. When HIGH, selects PCLK1, nPCLK1 inputs. When LOW, selects 12 CLK SEL Input Pulldown PCLK0, nPCLK0 inputs. Single-ended LVPECL interface levels. 13 PCLK0 Input Pulldown Non-inverting differential LVPECL clock input. Pullup/ 14 nPCLK0 Input Inverting differential LVPECL clock input. V /2 default when left floating. CC Pulldown 15 V Output Bias voltage. BB 16 PCLK1 Input Pulldown Non-inverting differential LVPECL clock input. Pullup/ 17 nPCLK1 Input Inverting differential LVPECL clock input. V /2 default when left floating. CC Pulldown 18, 20 V Power Positive supply pins. CC Synchronizing clock enable. When LOW, clock outputs follow clock input. When 19 Input Pulldown HIGH, Qx outputs are forced low, nQx outputs are forced high. nEN Single-ended LVPECL interface levels. NOTE: Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units R Input Pulldown Resistor 37 k PULLDOWN R Pullup/Pulldown Resistors 37 k VCC/2 ICS853S014AGI REVISION D MAY 23, 2013 2 2013 Integrated Device Technology, Inc.