Low Skew, 1-to-24, Differential-to-3.3V, 2.5V ICS853S024 LVPECL Fanout Buffer DATA SHEET General Description Features The ICS853S024 is a low skew, 1-to-24 Differential-to-3.3V, 2.5V Twenty four LVPECL outputs. LVPECL Fanout Buffer. The PCLK, nPCLK pair can accept most One differential clock input pair standard differential input levels. The ICS853S024 is characterized Differential input clock (PCLK, nPCLK) can accept the following to operate from either a 3.3V or a 2.5V power supply. Guaranteed signaling levels: LVDS, LVPECL, CML output skew characteristics make the ICS853S024 ideal for those Maximum output frequency: 2GHz clock distribution applications demanding well defined performance Translates any single ended input signal to 3.3V, 2.5V LVPECL and repeatability. levels with resistor bias on nPCLK input Output skew: 125ps (maximum) Rise and Fall Time: 180ps (typical) Additive phase jitter, RMS: 0.15ps (typical) 156.25MHz Full 3.3V or 2.5V supply voltage 0C to 70C ambient operating temperature Available in lead-free (RoHS 6) package Block Diagram Pin Assignment 24 Pulldown Q 0:23 PCLK 24 Pullup/Pulldown nPCLK nQ 0:23 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 V 1 48 nPCLK CC V EE 2 47 PCLK Q0 3 46 nQ17 nQ0 4 Q17 ICS853S024 45 Q1 5 44 nQ16 64-Lead TQFP, EPad nQ1 6 43 Q16 10mm x 10mm x 1mm Q2 7 42 nQ15 nQ2 8 41 Q15 package body Q3 9 40 nQ14 Y Package Q14 nQ3 10 39 Top View Q4 11 38 nQ13 nQ4 12 37 Q13 Q5 13 36 nQ12 Q12 nQ5 14 35 V 15 34 V EE CC V 16 V CC 33 CC 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ICS853S024AY REVISION A JULY 20, 2011 1 2011 Integrated Device Technology, Inc. VEE VCC VCC VCC Q6 nQ23 nQ6 Q23 Q7 nQ22 nQ7 Q22 Q8 nQ21 nQ8 Q21 Q9 nQ20 nQ9 Q20 Q10 nQ19 nQ10 Q19 Q11 nQ18 nQ11 Q18 VCC VCC VEE VEEICS853S024 Data Sheet LOW SKEW, 1-TO-24, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER Table 1. Pin Descriptions Number Name Type Description 1, 16, 18, 31, V Power Power supply pins. CC 33, 34, 50, 63, 64 2, 15, 17, 32, 49 V Power Negative supply pins. EE 3, 4 Q0, nQ0 Output Differential clock outputs. LVPECL interface levels. 5, 6 Q1, nQ1 Output Differential clock outputs. LVPECL interface levels. 7, 8 Q2, nQ2 Output Differential clock outputs. LVPECL interface levels. 9, 10 Q3, nQ3 Output Differential clock outputs. LVPECL interface levels. 11, 12 Q4, nQ4 Output Differential clock outputs. LVPECL interface levels. 13, 14 Q5, nQ5 Output Differential clock outputs. LVPECL interface levels. 19, 20 Q6, nQ6 Output Differential clock outputs. LVPECL interface levels. 21, 22 Q7, nQ7 Output Differential clock outputs. LVPECL interface levels. 23, 24 Q8, nQ8 Output Differential clock outputs. LVPECL interface levels. 25, 26 Q9, nQ9 Output Differential clock outputs. LVPECL interface levels. 27, 28 Q10, nQ10 Output Differential clock outputs. LVPECL interface levels. 29, 30 Q11, nQ11 Output Differential clock outputs. LVPECL interface levels. 35, 36 Q12, nQ12 Output Differential clock outputs. LVPECL interface levels. 37, 38 Q13, nQ13 Output Differential clock outputs. LVPECL interface levels. 39, 40 Q14, nQ14 Output Differential clock outputs. LVPECL interface levels. 41, 42 Q15, nQ15 Output Differential clock outputs. LVPECL interface levels. 43, 44 Q16, nQ16 Output Differential clock outputs. LVPECL interface levels. 45, 46 Q17, nQ17 Output Differential clock outputs. LVPECL interface levels. 47 PCLK Input Pulldown Non-inverting differential LVPECL clock input. Pullup/ Inverting differential LVPECL clock input. V /2 default when left CC 48 nPCLK Input floating. Pulldown 51, 52 Q18, nQ18 Output Differential clock outputs. LVPECL interface levels. 53, 54 Q19, nQ19 Output Differential clock outputs. LVPECL interface levels. 55, 56 Q20, nQ20 Output Differential clock outputs. LVPECL interface levels. 57, 58 Q21, nQ21 Output Differential clock outputs. LVPECL interface levels. 59, 60 Q22, nQ22 Output Differential clock outputs. LVPECL interface levels. 61, 62 Q23, nQ23 Output Differential clock outputs. LVPECL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 2pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN ICS853S024AY REVISION A JULY 20, 2011 2 2011 Integrated Device Technology, Inc.