nQ2 Q2 nQ1 VCCO Q1 nQ0 Q0 Low Skew, 1-to-8 Differential-to- ICS853S310I 3.3V LVPECL/ECL Fanout Buffer DATA SHEET General Description Features The ICS853S310I is a low skew, high performance 1-to-8 Eight differential 3.3V LVPECL/ECL outputs Differential-to-3.3V LVPECL/ECL Fanout Buffer. The PCLKx, Two selectable differential input pairs nPCLKx pairs can accept LVPECL, LVDS, CML and SSTL PCLKx, nPCLKx pairs can accept the following differential input levels. The ICS853S310I is characterized to operate differential input levels: LVPECL, LVDS, CML, SSTL from a 3.3V power supply. Guaranteed output and part-to-part skew Maximum output frequency: 2GHz characteristics make the ICS853S310I ideal for those clock Translates any single-ended input signal to 3.3V LVPECL levels distribution applications demanding well defined performance and with resistor bias on nPCLKx input repeatability. Output skew: 20ps (typical) Propagation delay: 825ps (typical) Additive phase jitter, RMS: 0.14ps (typical) LVPECL mode operating voltage supply range: V = 3.0V to 3.8V, V = 0V CC EE ECL mode operating voltage supply range: V = 0V, V = -3.0V to -3.8V CC EE -40C to 85C ambient operating temperature Available lead-free (RoHS 6) package Block Diagram Pin Assignment Pulldown PCLK0 0 Pullup/Pulldown nPCLK0 Q0 25 24 23 22 21 20 19 Pulldown nQ0 PCLK1 1 Pullup/Pulldown nPCLK1 26 Q3 VEE 18 Q1 CLK SEL 27 17 nQ3 nQ1 Pulldown CLK SEL PCLK0 16 Q4 28 Q2 V BB VCCO VCC 1 15 nQ2 nQ4 nPCLK0 2 14 Q3 VBB 3 13 Q5 nQ3 PCLK1 4 12 nQ5 Q4 5 6 7 8 9 10 11 nQ4 Q5 nQ5 ICS853S310I Q6 28-Lead PLCC nQ6 11.6mm x 11.4mm x 4.1mm package body Q7 V Package nQ7 Top View ICS853S310CVI REVISION A NOVEMBER 17, 2010 1 2010 Integrated Device Technology, Inc. nPCLK1 nc nQ7 VCCO Q7 nQ6 Q6ICS853S310I Data Sheet LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER Table 1. Pin Descriptions Number Name Type Description 1V Power Positive supply pin. CC Pullup/ 2 nPCLK0 Input Inverting differential LVPECL clock input. V /2 default when left floating. CC Pulldown 3V Output Bias voltage to be connected for single-ended applications. BB 4 PCLK1 Input Pulldown Non-inverting differential LVPECL clock input. Pullup/ 5 nPCLK1 Input Inverting differential LVPECL clock input. V /2 default when left floating. CC Pulldown 6 nc Unused No connect 7, 9 Output Differential output pair. LVPECL/ECL interface levels. nQ7, Q7 8, 15, 22 V Power Output supply pins. CCO 10, 11 Output Differential output pair. LVPECL/ECL interface levels. nQ6, Q6 12, 13 Output Differential output pair. LVPECL/ECL interface levels. nQ5, Q5 14, 16 Output Differential output pair. LVPECL/ECL interface levels. nQ4, Q4 17, 18 Output Differential output pair. LVPECL/ECL interface levels. nQ3, Q3 19, 20 Output Differential output pair. LVPECL/ECL interface levels. nQ2, Q2 21, 23 Output Differential output pair. LVPECL/ECL interface levels. nQ1, Q1 24, 25 Output Differential output pair. LVPECL/ECL interface levels. nQ0, Q0 26 V Power Negative supply pin. EE Clock select input. When HIGH, selects PCLK1, nPCLK1 inputs. When LOW, 27 CLK SEL Input Pulldown selects PCLK0, nPCLK0 inputs. LVPECL single-ended interface levels. Also accepts standard LVCMOS input levels. 28 PCLK0 Input Pulldown Non-inverting differential LVPECL clock input. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units R Input Pulldown Resistor 75 k PULLDOWN R Pullup/Pulldown Resistors 50 k VCC/2 ICS853S310CVI REVISION A NOVEMBER 17, 2010 2 2010 Integrated Device Technology, Inc.