Dual 2:1, 1:2 Differential-to-LVPECL/ 853S54I-01 ECL Multiplexer Datasheet Description Features The 853S54I-01 is a 2:1/1:2 Multiplexer. The 2:1 Multiplexer Dual 2:1, 1:2 MUX allows one of 2 inputs to be selected onto one output pin and the Three LVPECL output pairs 1:2 MUX switches one input to one of two outputs. This device may be useful for multiplexing multi-rate Ethernet PHYs which Three differential clock inputs can accept: LVPECL, LVDS, CML have 100Mbit and 1000Mbit transmit/receive pairs onto an optical Loopback test mode available RD SFP module which has a single transmit/receive pair. A 3 mode allows loop back testing and allows the output of a PHY transmit Maximum output frequency: 2.5GHz pair to be routed to the PHY input pair. For examples, please refer Propagation delay: 550ps (maximum) to the Application Block diagrams on pages 2-3 of the data sheet. Part-to-part skew: 275ps (maximum) The 853S54I-01 is optimized for applications requiring very high performance and has a maximum operating frequency in 2.5GHz. Additive phase jitter, RMS: 27fs (typical) The device is packaged in a small, 3mm x 3mm VFQFN package, making it ideal for use on space-constrained boards. LVPECL mode operating voltage supply range: V = 2.375V to 3.465V, V = 0V CC EE ECL mode operating voltage supply range: V = 0V, V = -3.465V to -2.375V CC EE -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Block Diagram Pin Assignment SELB 16 15 14 13 1 QA0 12 INA0 Pulldown 2 11 nQA0 nINA0 INA0 Pullup/Pulldown 3 10 QA1 INA1 nINA0 nQA1 4 nINA1 9 5 6 7 8 Pulldown INB LOOP 0 0 Pullup/Pulldown nINB QA0 nQA0 853S54I-01 1 16-Lead VFQFN 0 QB 3mm x 3mm x 0.925mm Pulldown nQB INA1 package body 1 Pullup/Pulldown nINA1 K Package Top View LOOP 1 QA1 nQA1 SELA 2017 Integrated Device Technology, Inc. 1 June 16, 2017 Pulldown Pulldown INB QB nINB nQB SELB SELA VEE VCC853S54I-01 Datasheet Table 1. Pin Descriptions Number Name Type Description 1, 2 QA0, nQA0 Output Differential output pair. LVPECL/ECL interface levels. 3, 4 QA1, nQA1 Output Differential output pair. LVPECL/ECL interface levels. 5 INB Input Pulldown Non-inverting LVPECL/ECL differential clock input. Pullup/ 6 nINB Input Inverting LVPECL differential clock input. V /2 default when left floating. CC Pulldown 7 SELB Input Pulldown Select pin for QB output. See Table 3. LVCMOS/LVTTL interface levels. 8V Power Negative supply pin. EE Pullup/ 9 nINA1 Input Inverting differential LVPECL clock input. V /2 default when left floating. CC Pulldown 10 INA1 Input Pulldown Non-inverting differential LVPECL clock input. Pullup/ 11 nINA0 Input Inverting differential LVPECL clock input. V /2 default when left floating. CC Pulldown 12 INA0 Input Pulldown Non-inverting differential clock input. 13 V Power Power supply pin. CC 14 SELA Input Pulldown Select pin for QAx outputs. See Table 3. LVCMOS/LVTTL interface levels. 15, 16 nQB, QB Output Differential output pair. LVPECL/ECL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units R Input Pullup Resistor 37.5 k PULLUP R Input Pulldown Resistor 37.5 k PULLDOWN Function Tables Table 3. Control Input Function Table Control Inputs SELA SELB Mode 0 0 LOOP 0 selected 1 0 LOOP 1 selected 0 1 Loopback mode: LOOP 0 1 1 Loopback mode: LOOP 1 2017 Integrated Device Technology, Inc. 2 June 16, 2017