2.5V, 3.3V ECL/LVPECL Clock/Data ICS853S9252I Fanout Buffer DATASHEET General Description Features The ICS853S9252I is a 2.5V/3.3V ECL/LVPECL fanout buffer 1:2 differential clock/data fanout buffer designed for high-speed, low phase-noise wireless infrastructure Clock frequency: 3GHz (maximum) applications. The device fanouts a differential input signal to two Two differential 2.5V/3.3V ECL/LVPECL clock output ECL/LVPECL outputs. Optimized for low additive phase-noise, Differential input accepts ECL/LVPECL, LVDS and CML levels sub-100ps output rise and fall times, low output skew and high-frequencies, the ICS853S9252I is an effective solution for Additive phase jitter, RMS 122.88MHz: 45fs (typical) high-performance clock and data distribution applications, for Propagation delay: 175ps (maximum), V = 3.3V CC instance driving the reference clock inputs of ADC/DAC circuits. Output rise/fall time: 135ps (maximum), V = 3.3V CC Internal input termination, a bias voltage output (V ) for REF Internal input signal termination AC-coupling and small packaging (3.0mm x 3.0mm 16-lead VFQFN) supports space-efficient board designs. Supply voltage: 2.5V-5% to 3.3V+10% Lead-free (RoHS 6) packaging The ICS853S9252I operates from a full 2.5V or 3.3V power supply -40C to 85C ambient operating temperature and supports the industrial temperature range of -40C to 85C. The extended temperature range also supports wireless infrastructure, tele-communication and networking end equipment requirements. Block Diagram Pin Assignment Q0 nQ0 IN nIN Q1 16 15 14 13 12 Q0 IN 1 nQ1 50 50 11 nQ0 nIN 2 10 Q1 nc 3 VTT 9 nQ1 nc 4 5 6 7 8 VREF VREF Generator ICS853S9252I 16 lead VFQFN 3.0mm x 3.0mm x 0.925mm package body K Package Top View ICS853S9252BKI JUNE 14, 2017 1 2017 Integrated Device Technology, Inc. nc VTT nc VREF V V EE EE VCC V CCICS853S9252I Datasheet 2.5V, 3.3V ECL/LVPECL CLOCK/DATA FANOUT BUFFER Pin Descriptions Table 1. Pin Descriptions Number Name Type Description Non-inverting and inverting clock input. ECL/LVPECL, LVDS and CML interface levels. 50 1, 2 IN, nIN Input or 100 input termination. to V TT 3, 4, 5, 6 nc Unused No connect. Power Negative supply pins. 7, 14 V EE Power Power supply pins. 8, 13 V CC 9, 10 nQ1, Q1 Output Differential clock output. ECL/LVPECL interface levels. 11, 12 nQ0, Q0 Output Differential clock output. ECL/LVPECL interface levels. Output Bias voltage reference for AC-coupling of the differential inputs. 15 V REF Center tap for input termination. Leave floating for LVDS inputs, connect 50 to GND for 16 V TT 3.3V LVPECL inputs and to the V output for AC-coupled applications. REF Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, V 4.6V (LVPECL mode, V = 0V) CC EE -4.6V (ECL mode, V = 0V) Negative Supply Voltage, V EE CC (LVPECL mode) -0.5V to V + 0.5V Inputs, V I CC (ECL mode) 0.5V to V 0.5V Inputs, V I EE Outputs, I O Continuous Current 50mA Surge Current 100mA Input Current, IN, nIN 25mA Current, I 50mA V T VT 2mA Input Sink/Source, I REF -40C to +85C Operating Temperature Range, T A , (Junction-to-Ambient) 74.7C/W (0 mps) Package Thermal Impedance, JA -65C to 150C Storage Temperature, T STG ICS853S9252BKI JUNE 14, 2017 2 2017 Integrated Device Technology, Inc.