VDD nQ0 Low Skew, 1-to-8, Differential-to-LVDS 85408 Clock DATA SHEET General Description Features The 85408 is a low skew, high performance 1-to-8 Eight differential LVDS output pairs Differential-to-LVDS Clock Distribution Chip. The 85408 CLK, nCLK CLK/nCLK can accept the following differential input levels: pair can accept most differential input levels and translates them to LVPECL, LVDS, LVHSTL, HCSL, SSTL 3.3V LVDS output levels. Utilizing Low Voltage Differential Signaling Maximum output frequency: 700MHz (LVDS), the 85408 provides a low power, low noise, low skew, Translates any differential input signal (LVPECL, LVHSTL, SSTL, point-to-point solution for distributing LVDS clock signals. HCSL) to LVDS levels without external bias networks Guaranteed output and part-to-part skew specifications make the Translates any single-ended input signal to LVDS with resistor 85408 ideal for those applications demanding well defined bias on nCLK input performance and repeatability. Output skew: 50ps (maximum) Part-to-part skew: 550ps (maximum) Propagation delay: 2.4ns (maximum) 3.3V operating supply 0C to 70C ambient operating temperature Available in lead-free (RoHS 6) package Block Diagram Pin Assignment OE 1 24 Q7 nQ6 Q6 2 23 nQ7 Q0 nQ5 3 22 OE nQ0 Q5 4 21 GND Q1 nQ4 5 20 VDD nQ1 6 19 VDD Q4 nQ3 7 18 GND Q2 Q3 8 17 nQ2 nQ2 9 16 CLK Q3 Q2 10 15 nCLK nQ3 CLK nQ1 Q0 11 14 nCLK Q4 Q1 12 13 nQ4 85408 Q5 nQ5 24-Lead TSSOP Q6 4.4mm x 7.8mm x 0.925mm package body nQ6 G Package Q7 Top View nQ7 85408 Rev C 1/5/15 1 2015 Integrated Device Technology, Inc.85408 DATA SHEET Table 1. Pin Descriptions Number Name Type Description 1, 2 nQ6, Q6 Output Differential output pair. LVDS interface levels. 3, 4 nQ5, Q5 Output Differential output pair. LVDS interface levels. 5, 6 nQ4, Q4 Output Differential output pair. LVDS interface levels. 7, 8 nQ3, Q3 Output Differential output pair. LVDS interface levels. 9, 10 nQ2, Q2 Output Differential output pair. LVDS interface levels. 11, 12 nQ1, Q1 Output Differential output pair. LVDS interface levels. 13, 14 nQ0, Q0 Output Differential output pair. LVDS interface levels. 15 nCLK Input Pullup Inverting differential clock input. 16 CLK Input Pulldown Non-inverting differential clock input. 17, 19, 20 V Power Positive supply pins. DD 18, 21 GND Power Power supply ground. Output enable. Controls the enabling and disabling of outputs Qx, nQx. When HIGH, 22 OE Input Pullup the outputs are enabled. When LOW, the outputs are in High-Impedance. LVCMOS / LVTTL interface levels. 23, 24 nQ7, Q7 Output Differential output pair. LVDS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4pF IN Power Dissipation Capacitance C 4pF PD (per output) R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN Function Tables Table 3A. Output Enable Function Table Inputs Outputs OE Q 0:7 , nQ 0:7 0 High-Impedance 1 Active (default) Rev C 1/5/15 2 LOW SKEW, 1-TO-8, DIFFERENTIAL-TO-LVDS CLOCK