8732AYI-01LF Renesas

VCC VCCO DIV SELB0 QFB1 DIV SELB1 nQFB1 nc QFB0 VCCA nQFB0 CLK SEL VEE CLK0 VCC nCLK0 FB IN CLK1 nFB IN VEE FBDIV SEL0 VCC FBDIV SEL1 DIV SELA0 FBDIV SEL2 DIV SELA1 VEE Low Voltage, Low Skew, 3.3V LVPECL ICS8732I-01 Clock Generator DATA SHEET GENERAL DESCRIPTION Features Ten differential 3.3V LVPECL output pairs The ICS8732I-01 is a low voltage, low skew, ICS 3.3V LVPECL Clock Generator. The ICS8732I- Selectable differential CLK0, nCLK0 or LVCMOS/LVTTL CLK1 HiPerClockS 01 has two selectable clock inputs. The CLK0, inputs nCLK0 pair can accept most standard differ- CLK0, nCLK0 supports the following input types: LVPECL, ential input levels. The single ended clock in- LVDS, LVHSTL, SSTL, HCSL put accepts LVCMOS or LVTTL input levels. The ICS8732I- CLK1 accepts the following input levels: LVCMOS or LVTTL 01 has a fully integrated PLL along with frequency configurable outputs. An external feedback input and out- Maximum output frequency: 350MHz puts regenerate clocks with zero delay. VCO range: 250MHz to 700MHz The ICS8732I-01 has multiple divide select pins for each External feedback for zero delay clock regeneration with bank of outputs along with 3 independent feedback divide configurable frequencies select pins allowing the ICS8732I-01 to function both as a Cycle-to-cycle jitter: CLK0, nCLK0, 50ps (maximum), frequency multiplier and divider. The PLL SEL input can CLK1, 80ps (maximum) be used to bypass the PLL for test and system debug pur- Output skew: 75ps (maximum) poses. In bypass mode, the input clock is routed around the PLL and into the internal output dividers. Static phase offset: -100ps to 200ps Full 3.3V supply mode -40C to 85C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages BLOCK DIAGRAM PIN ASSIGNMENT CLK SEL CLK0 0 QA0 nCLK0 0 2 4 6 8 nQA0 52 51 50 49 48 47 46 45 44 43 42 41 40 1 2 4 8 12 CLK1 PLL 1 VCCO 1 39 VCCO QA1 nQA1 QA0 2 38 nQB3 FB IN 4 6 8 10 nFB IN 8 12 16 20 QA2 nQA0 3 37 QB3 nQA2 QA1 4 36 nQB2 QA3 nQA1 5 35 QB2 nQA3 PLL SEL VEE 6 34 VEE PLL SEL QB0 7 33 MR ICS8732I-01 DIV SELA0 nQB0 VCCO 8 32 VCCO DIV SELA1 QB1 QA2 9 31 nQB1 nQB1 DIV SELB0 nQA2 10 30 QB1 QB2 DIV SELB1 nQB2 QA3 11 29 nQB0 FBDIV SEL0 nQA3 QB3 12 28 QB0 FBDIV SEL1 nQB3 VEE 13 27 VEE FBDIV SEL2 14 15 16 17 18 19 20 21 22 23 24 25 26 QFB0 nQFB0 QFB1 nQFB1 52-Lead LQFP MR 10mm x 10mm x 1.4mm package body Y package Top View ICS8732AYI-01 REVISION A NOVEMBER 10, 2009 1 2009 Integrated Device Technology, Inc.ICS8732I-01 Data Sheet LOW VOLTAGE, LOW SKEW, 3.3V LVPECL CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS NeumberNeam Tnyp Descriptio 1V, 8, 32, 39, 40 P.ower Output supply pins CCO 2, 3, QA0, nQA0, O.utput Differential output pair. LVPECL interface levels 4, 5 QA1, nQA1 6, 13, 17, 27, VP.ower Negative supply pins EE 34, 45, 52 Selects between the PLL and reference clock as the input to the dividers. 7LPtLL SE Ipnpu Pullu When LOW, selects reference clock. When HIGH, selects PLL. LVCMOS / LVTTL interface levels. 9, 10, 1 QA2, nQA2, O.utput Differential output pairs. LVPECL interface levels 1, 12 QA3, nQA3 Determines output divider valued in Table 3. 114 DtIV SELAInnpu Pulldow LVCMOS / LVTTL interface levels. Determines output divider valued in Table 3. 105DtIV SELAInnpu Pulldow LVCMOS / LVTTL interface levels. 1V6, 26, 46 P.ower Core supply pins CC 118 CtLK InnpuP.ulldow LVCMOS / LVTTL reference clock input 109 ntCLK IpnpuP.ullu Inverting differential clock input 200 CtLK InnpuP.ulldow Non-inverting differential clock input Clock select input. When LOW, selects CLK0, nCLK0. 2L1 CtLK SEInnpu Pulldow When HIGH, selects CLK1. LVCMOS / LVTTL interface levels. 2V2 P.ower Analog supply pin CCA 2c3 ndU.nuse No connect Determines output divider valued in Table 3. 214 DtIV SELBInnpu Pulldow LVCMOS / LVTTL interface levels. Determines output divider valued in Table 3. 205DtIV SELBInnpu Pulldow LVCMOS / LVTTL interface levels. 28, 29, QB0, nQB0, O.utput Differential output pairs. LVPECL interface levels 30, 31 QB1, nQB1 Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inverted outputs 3R3 MtInnpu Pulldow nQx to go high. When LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. 35, 36, QB2, nQB2, O.utput Differential output pairs. LVPECL interface levels 37, 38 QB3, nQB3 41, 42, QFB1, nQFB1, Output Differential feedback output pairs. LVPECL interface levels. 43, 44 QFB0, nQFB0 Feedback input to phase detector for regenerating clocks 4N7 FtB I Innpu Pulldow withzero dela. Feedback input to phase detector for regenerating clocks 4N8 ntFB I Ipnpu Pullu withzero dela. Selects divide value for differential feedback output pairs. 409FtBDIV SELInnpu Pulldow LVCMOS / LVTTL interface levels. Selects divide value for differential feedback output pairs. 510FtBDIV SELInnpu Pulldow LVCMOS / LVTTL interface levels. Selects divide value for differential feedback output pairs. 521FtBDIV SELInnpu Pulldow LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. ICS8732AYI-01 REVISION A NOVEMBER 10, 2009 2 2009 Integrated Device Technology, Inc.